yosys/tests/errors/syntax_err05.v at 3d15712a3b6c76dd26150cc3d9855bbe698b862c - mirrors/yosys - Libre-Chip.org

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Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.

2018-10-25 02:37:56 +03:00

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35 B

Verilog

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 module a;
 input x[2:0];
 endmodule