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81964d6d6f
* remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style
24 lines
937 B
Text
24 lines
937 B
Text
read_verilog ../common/mux.v
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design -save read
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design -load read
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hierarchy -top mux4
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proc
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equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-max 1 t:CC_LUT2
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select -assert-max 2 t:CC_LUT4
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select -assert-max 1 t:CC_MX2
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select -assert-none t:CC_LUT2 t:CC_LUT4 t:CC_MX2 %% t:* %D
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design -load read
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hierarchy -top mux8
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proc
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equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-max 1 t:CC_LUT3
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select -assert-max 5 t:CC_LUT4
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select -assert-max 1 t:CC_MX2
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select -assert-none t:CC_LUT3 t:CC_LUT4 t:CC_MX2 %% t:* %D
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