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2e37e62e6b
By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
57 lines
1.5 KiB
Verilog
57 lines
1.5 KiB
Verilog
module \$lut (A, Y);
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parameter WIDTH = 1;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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generate
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if (LUT == 2'b00) begin
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assign Y = 1'b0;
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end
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else if (LUT == 2'b01) begin
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MISTRAL_NOT _TECHMAP_REPLACE_(
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.A(A[0]), .Q(Y)
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);
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end
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else if (LUT == 2'b10) begin
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assign Y = A;
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end
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else if (LUT == 2'b11) begin
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assign Y = 1'b1;
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end
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endgenerate
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end else
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if (WIDTH == 2) begin
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MISTRAL_ALUT2 #(.LUT(LUT)) _TECHMAP_REPLACE_(
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.A(A[0]), .B(A[1]), .Q(Y)
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);
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end else
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if (WIDTH == 3) begin
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MISTRAL_ALUT3 #(.LUT(LUT)) _TECHMAP_REPLACE_(
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.A(A[0]), .B(A[1]), .C(A[2]), .Q(Y)
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);
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end else
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if (WIDTH == 4) begin
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MISTRAL_ALUT4 #(.LUT(LUT)) _TECHMAP_REPLACE_(
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.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .Q(Y)
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);
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end else
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if (WIDTH == 5) begin
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MISTRAL_ALUT5 #(.LUT(LUT)) _TECHMAP_REPLACE_ (
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.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .Q(Y)
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);
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end else
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if (WIDTH == 6) begin
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MISTRAL_ALUT6 #(.LUT(LUT)) _TECHMAP_REPLACE_ (
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.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .Q(Y)
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);
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end else begin
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wire _TECHMAP_FAIL_ = 1'b1;
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end
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endgenerate
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endmodule
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