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yosys
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techlibs
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xilinx
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..
tests
.gitignore
abc9_model.v
arith_map.v
brams_init.py
cells_map.v
cells_sim.v
cells_xtra.py
cells_xtra.v
lut4_lutrams.txt
lut6_lutrams.txt
lut_map.v
lutrams_map.v
Makefile.inc
mux_map.v
synth_xilinx.cc
xc2v_brams.txt
xc2v_brams_map.v
xc3s_mult_map.v
xc3sa_brams.txt
xc3sda_brams.txt
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_brams.txt
xc6s_brams_map.v
xc6s_dsp_map.v
xc6s_ff_map.v
xc7_brams_map.v
xc7_dsp_map.v
xc7_ff_map.v
xc7_xcu_brams.txt
xcu_brams_map.v
xcu_dsp_map.v
xcup_urams.txt
xcup_urams_map.v
xilinx_dffopt.cc