Miodrag Milanovic e6f7cf3b29 Update tests		2023-06-09 14:41:45 +02:00
..
.gitignore
abc9_dff.ys	Fix tests for check in equiv_opt	2022-10-07 16:04:51 +02:00
add_sub.ys
adffs.ys
asym_ram_sdp.ys	Asymmetric port ram tests with Xilinx	2023-02-21 05:23:14 +13:00
asym_ram_sdp_read_wider.v	Asymmetric port ram tests with Xilinx	2023-02-21 05:23:14 +13:00
asym_ram_sdp_write_wider.v	Asymmetric port ram tests with Xilinx	2023-02-21 05:23:14 +13:00
attributes_test.ys	xilinx: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
blockram.ys	xilinx: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
bug1460.ys
bug1462.ys
bug1480.ys
bug1598.ys
bug1605.ys
bug3670.v	ABC9: Cell Port Bug Patch (#3670)	2023-04-22 16:24:36 -07:00
bug3670.ys	ABC9: Cell Port Bug Patch (#3670)	2023-04-22 16:24:36 -07:00
counter.ys
dffs.ys
dsp_abc9.ys	Add ABC9 DSP cascade test	2023-05-25 18:42:08 +01:00
dsp_cascade.ys
dsp_fastfir.ys
dsp_simd.ys
fsm.ys
latches.ys
logic.ys
lutram.ys	xilinx: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
macc.sh
macc.v
macc.ys
macc_tb.v
mul.ys
mul_unsigned.v
mul_unsigned.ys
mux.ys
mux_lut4.ys	Update tests	2023-06-09 14:41:45 +02:00
nosrl.ys
opt_lut_ins.ys	Fix tests for check in equiv_opt	2022-10-07 16:04:51 +02:00
pmgen_xilinx_srl.ys
priority_memory.v	Tests for ram_style = "huge"	2023-02-21 05:23:15 +13:00
priority_memory.ys	Tests for ram_style = "huge"	2023-02-21 05:23:15 +13:00
run-test.sh
shifter.ys
tribuf.sh	Fix the tests we just broke	2021-12-10 00:22:37 +01:00
tribuf.ys
xilinx_dffopt.ys	Fix tests for check in equiv_opt	2022-10-07 16:04:51 +02:00
xilinx_dffopt_blacklist.txt
xilinx_dsp.ys
xilinx_srl.v
xilinx_srl.ys