Clifford Wolf ea82191c57 Add inout ports to cells_xtra.v ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2018-10-08 11:38:10 -07:00
..
tests
.gitignore
arith_map.v
brams.txt
brams_bb.v
brams_init.py	Squelch trailing whitespace, including meta-whitespace	2018-03-11 16:03:41 +01:00
brams_map.v
cells_map.v	Improving vpr output support.	2018-04-18 16:55:12 -07:00
cells_sim.v
cells_xtra.sh	Add inout ports to cells_xtra.v	2018-10-08 11:38:10 -07:00
cells_xtra.v	Add inout ports to cells_xtra.v	2018-10-08 11:38:10 -07:00
drams.txt
drams_map.v
lut2lut.v
Makefile.inc
synth_xilinx.cc	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00