| .. | 
		
		
			
			
			
			
				| .gitignore | added more .gitignore files (make test) | 2013-01-05 11:35:52 +01:00 | 
		
			
			
			
			
				| aes_kexp128.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| always01.v | Added test cases from 2012 paper on comparison of foss verilog synthesis tools | 2013-03-31 11:17:56 +02:00 | 
		
			
			
			
			
				| always02.v | Added test cases from 2012 paper on comparison of foss verilog synthesis tools | 2013-03-31 11:17:56 +02:00 | 
		
			
			
			
			
				| always03.v | Added test cases from 2012 paper on comparison of foss verilog synthesis tools | 2013-03-31 11:17:56 +02:00 | 
		
			
			
			
			
				| arrays01.v | Added test cases from 2012 paper on comparison of foss verilog synthesis tools | 2013-03-31 11:17:56 +02:00 | 
		
			
			
			
			
				| dff_different_styles.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| fiedler-cooley.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| forgen01.v | Added test cases from 2012 paper on comparison of foss verilog synthesis tools | 2013-03-31 11:17:56 +02:00 | 
		
			
			
			
			
				| forgen02.v | Added test cases from 2012 paper on comparison of foss verilog synthesis tools | 2013-03-31 11:17:56 +02:00 | 
		
			
			
			
			
				| fsm.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| generate.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| i2c_master_tests.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| loops.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| mem2reg.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| mem_arst.v | Renamed hansimem.v test case to mem_arst.v | 2013-03-24 15:25:08 +01:00 | 
		
			
			
			
			
				| memory.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| muxtree.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| omsp_dbg_uart.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| operators.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| paramods.v | Added defparam support to Verilog/AST frontend | 2013-07-04 14:12:33 +02:00 | 
		
			
			
			
			
				| process.v | Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values | 2013-04-13 21:19:10 +02:00 | 
		
			
			
			
			
				| run-test.sh | added ckeck for Icarus Verilog, otherwise the tests are silently stopped | 2013-03-17 09:05:15 +01:00 | 
		
			
			
			
			
				| signedexpr.v | Major redesign of expr width/sign detecion (verilog/ast frontend) | 2013-07-09 14:31:57 +02:00 | 
		
			
			
			
			
				| subbytes.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| task_func.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| usb_phy_tetsts.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| values.v | initial import | 2013-01-05 11:13:26 +01:00 | 
		
			
			
			
			
				| vloghammer.v | More fixes in ternary op sign handling | 2013-07-12 13:13:04 +02:00 |