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Code Activity
yosys/backends
History
Jim Lawson 3b8c917025 Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences. 
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
2019-07-31 09:27:38 -07:00
..
aiger Rename __builtin_bswap32 -> bswap32 2019-07-09 09:35:09 -07:00
blif Fix handling of offset and upto module ports in write_blif, fixes #1040 2019-05-25 17:45:14 +02:00
btor Merge origin/master 2019-06-27 11:20:15 -07:00
edif Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
firrtl Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences. 2019-07-31 09:27:38 -07:00
ilang Allow attributes on individual switch cases in RTLIL. 2019-07-08 11:34:58 +00:00
intersynth Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
json Fix json formatting 2019-06-21 20:01:40 +02:00
protobuf Support filename rewrite in backends 2019-06-18 14:39:52 -07:00
simplec Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
smt2 smt: handle failure of setrlimit syscall 2019-07-15 23:33:18 +08:00
smv Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
spice Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
table Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
verilog Merge pull request #1203 from whitequark/write_verilog-zero-width-values 2019-07-18 15:31:27 +02:00