Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing ... for signed attributes Co-authored-by: N. Engelhardt <nak@yosyshq.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>		2024-09-10 12:52:42 +02:00
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.gitignore
bounds.vhd	Add left and right bound properties to wire. Add test. Fix printing	2024-09-10 12:52:42 +02:00
bounds.ys	Add left and right bound properties to wire. Add test. Fix printing	2024-09-10 12:52:42 +02:00
case.sv
case.ys
clocking.ys
enum_values.sv
enum_values.ys
memory_semantics.ys
range_case.sv
range_case.ys
rom_case.ys
run-test.sh