mirror of
https://github.com/YosysHQ/yosys
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255 lines
10 KiB
C++
255 lines
10 KiB
C++
/* -*- c++ -*-
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 Alberto Gonzalez <boqwxp@airmail.cc>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef QBFSAT_H
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#define QBFSAT_H
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#include "kernel/yosys.h"
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#include <numeric>
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YOSYS_NAMESPACE_BEGIN
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struct QbfSolveOptions {
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bool specialize = false, specialize_from_file = false, write_solution = false, nocleanup = false;
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bool dump_final_smt2 = false, assume_outputs = false, assume_neg = false, nooptimize = false;
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bool nobisection = false, sat = false, unsat = false, show_smtbmc = false;
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enum Solver{Z3, Yices, CVC4, CVC5} solver = Yices;
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enum OptimizationLevel{O0, O1, O2} oflag = O0;
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dict<std::string, std::string> solver_options;
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int timeout = 0;
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std::string specialize_soln_file = "";
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std::string write_soln_soln_file = "";
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std::string dump_final_smt2_file = "";
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size_t argidx = 0;
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std::string get_solver_name() const {
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if (solver == Solver::Z3)
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return "z3";
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else if (solver == Solver::Yices)
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return "yices";
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else if (solver == Solver::CVC4)
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return "cvc4";
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else if (solver == Solver::CVC5)
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return "cvc5";
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log_cmd_error("unknown solver specified.\n");
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return "";
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}
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};
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struct QbfSolutionType {
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std::vector<std::string> stdout_lines = {};
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dict<pool<std::string>, std::string> hole_to_value = {};
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double solver_time = 0;
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bool sat = false;
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bool unknown = true; //true if neither 'sat' nor 'unsat'
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dict<std::pair<pool<std::string>, int>, RTLIL::SigBit> get_hole_loc_idx_sigbit_map(RTLIL::Module *module) const {
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dict<std::pair<pool<std::string>, int>, RTLIL::SigBit> hole_loc_idx_to_sigbit;
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pool<RTLIL::SigBit> anyconst_sigbits;
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dict<RTLIL::SigBit, RTLIL::SigBit> anyconst_sigbit_to_wire_sigbit;
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for (auto cell : module->cells()) {
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pool<std::string> cell_src = cell->get_strpool_attribute(ID::src);
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auto pos = hole_to_value.find(cell_src);
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if (pos != hole_to_value.end() && cell->type.in("$anyconst", "$anyseq")) {
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RTLIL::SigSpec port_y = cell->getPort(ID::Y);
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for (int i = GetSize(port_y) - 1; i >= 0; --i) {
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hole_loc_idx_to_sigbit[std::make_pair(pos->first, i)] = port_y[i];
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anyconst_sigbits.insert(port_y[i]);
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}
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}
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}
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for (auto &conn : module->connections()) {
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auto lhs = conn.first;
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auto rhs = conn.second;
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for (auto i = 0; i < GetSize(rhs); ++i) {
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if (anyconst_sigbits[rhs[i]]) {
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auto pos = anyconst_sigbit_to_wire_sigbit.find(rhs[i]);
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if (pos != anyconst_sigbit_to_wire_sigbit.end())
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log_cmd_error("conflicting names for hole $anyconst sigbit %s\n", log_signal(rhs[i]));
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anyconst_sigbit_to_wire_sigbit[rhs[i]] = lhs[i];
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}
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}
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}
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for (auto &it : hole_loc_idx_to_sigbit) {
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auto pos = anyconst_sigbit_to_wire_sigbit.find(it.second);
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if (pos != anyconst_sigbit_to_wire_sigbit.end())
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it.second = pos->second;
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}
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return hole_loc_idx_to_sigbit;
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}
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void dump_model(RTLIL::Module *module) const {
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log("Satisfiable model:\n");
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auto hole_loc_idx_to_sigbit = get_hole_loc_idx_sigbit_map(module);
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for (auto &it : hole_to_value) {
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pool<std::string> hole_loc = it.first;
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std::string hole_value = it.second;
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for (unsigned int i = 0; i < hole_value.size(); ++i) {
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int bit_idx = GetSize(hole_value) - 1 - i;
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auto it = hole_loc_idx_to_sigbit.find(std::make_pair(hole_loc, i));
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log_assert(it != hole_loc_idx_to_sigbit.end());
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RTLIL::SigBit hole_sigbit = it->second;
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log("\t%s = 1'b%c\n", log_signal(hole_sigbit), hole_value[bit_idx]);
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}
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}
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}
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void write_solution(RTLIL::Module *module, const std::string &file) const {
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std::ofstream fout(file.c_str());
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if (!fout)
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log_cmd_error("could not open solution file for writing.\n");
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//There is a question here: How exactly shall we identify holes?
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//There are at least two reasonable options:
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//1. By the source location of the $anyconst cells
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//2. By the name(s) of the wire(s) connected to each SigBit of the $anyconst cell->getPort(ID::Y) SigSpec.
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//
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//Option 1 has the benefit of being very precise. There is very limited potential for confusion, as long
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//as the source attribute has been set. However, if the source attribute is not set, this won't work.
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//More importantly, we want to have the ability to port hole assignments to other modules with compatible
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//hole names and widths. Obviously in those cases source locations of the $anyconst cells will not match.
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//
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//Option 2 has the benefits previously described, but wire names can be changed automatically by
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//optimization or techmapping passes, especially when (ex/im)porting from BLIF for optimization with ABC.
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//
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//The approach taken here is to allow both options. We write the assignment information for each bit of
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//the solution on a separate line. Each line is of one of two forms:
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//
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//location bit name = value
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//location bit name [offset] = value
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//
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//where '[', ']', and '=' are literal symbols, "location" is the $anyconst cell source location attribute,
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//"bit" is the index of the $anyconst cell, "name" is the `wire->name` field of the SigBit corresponding
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//to the current bit of the $anyconst cell->getPort(ID::Y), "offset" is the `offset` field of that same
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//SigBit, and "value", which is either '0' or '1', represents the assignment for that bit.
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auto hole_loc_idx_to_sigbit = get_hole_loc_idx_sigbit_map(module);
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for (auto &x : hole_to_value) {
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std::string src_as_str = std::accumulate(x.first.begin(), x.first.end(), std::string(), [](const std::string &a, const std::string &b){return a + "|" + b;});
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for (auto i = 0; i < GetSize(x.second); ++i)
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fout << src_as_str.c_str() << " " << i << " " << log_signal(hole_loc_idx_to_sigbit[std::make_pair(x.first, i)]) << " = " << x.second[GetSize(x.second) - 1 - i] << std::endl;
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}
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}
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void recover_solution() {
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std::regex sat_regex = YS_REGEX_COMPILE("Status: PASSED");
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std::regex unsat_regex = YS_REGEX_COMPILE("Solver Error.*model is not available");
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std::regex unsat_regex2 = YS_REGEX_COMPILE("Status: FAILED");
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std::regex timeout_regex = YS_REGEX_COMPILE("No solution found! \\(timeout\\)");
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std::regex timeout_regex2 = YS_REGEX_COMPILE("No solution found! \\(interrupted\\)");
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std::regex unknown_regex = YS_REGEX_COMPILE("No solution found! \\(unknown\\)");
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std::regex unknown_regex2 = YS_REGEX_COMPILE("Unexpected EOF response from solver");
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std::regex memout_regex = YS_REGEX_COMPILE("Solver Error:.*error \"out of memory\"");
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std::regex hole_value_regex = YS_REGEX_COMPILE_WITH_SUBS("Value for anyconst in [a-zA-Z0-9_]* \\(([^:]*:[^\\)]*)\\): (.*)");
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#ifndef NDEBUG
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std::regex hole_loc_regex = YS_REGEX_COMPILE("[^:]*:[0-9]+.[0-9]+-[0-9]+.[0-9]+");
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std::regex hole_val_regex = YS_REGEX_COMPILE("[0-9]+");
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#endif
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std::smatch m;
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bool sat_regex_found = false;
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bool unsat_regex_found = false;
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dict<std::string, bool> hole_value_recovered;
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for (const std::string &x : stdout_lines) {
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if(std::regex_search(x, m, hole_value_regex)) {
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std::string loc = m[1].str();
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std::string val = m[2].str();
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#ifndef NDEBUG
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log_assert(std::regex_search(loc, hole_loc_regex));
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log_assert(std::regex_search(val, hole_val_regex));
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#endif
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auto locs = split_tokens(loc, "|");
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pool<std::string> loc_pool(locs.begin(), locs.end());
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hole_to_value[loc_pool] = val;
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}
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else if (std::regex_search(x, sat_regex)) {
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sat_regex_found = true;
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sat = true;
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unknown = false;
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}
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else if (std::regex_search(x, unsat_regex)) {
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unsat_regex_found = true;
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sat = false;
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unknown = false;
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}
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else if (std::regex_search(x, memout_regex)) {
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unknown = true;
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log_warning("solver ran out of memory\n");
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}
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else if (std::regex_search(x, timeout_regex)) {
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unknown = true;
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log_warning("solver timed out\n");
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}
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else if (std::regex_search(x, timeout_regex2)) {
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unknown = true;
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log_warning("solver timed out\n");
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}
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else if (std::regex_search(x, unknown_regex)) {
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unknown = true;
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log_warning("solver returned \"unknown\"\n");
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}
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else if (std::regex_search(x, unsat_regex2)) {
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unsat_regex_found = true;
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sat = false;
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unknown = false;
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}
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else if (std::regex_search(x, unknown_regex2)) {
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unknown = true;
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}
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}
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log_assert(!unknown && sat? sat_regex_found : true);
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log_assert(!unknown && !sat? unsat_regex_found : true);
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}
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};
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void print_proof_failed()
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{
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log("\n");
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log(" ______ ___ ___ _ _ _ _ \n");
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log(" (_____ \\ / __) / __) (_) | | | |\n");
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log(" _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | |\n");
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log(" | ____/ ___) _ \\ / _ (_ __) (_ __|____ | | || ___ |/ _ |_|\n");
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log(" | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ \n");
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log(" |_| |_| \\___/ \\___/ |_| |_| \\_____|_|\\_)_____)\\____|_|\n");
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log("\n");
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}
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void print_qed()
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{
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log("\n");
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log(" /$$$$$$ /$$$$$$$$ /$$$$$$$ \n");
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log(" /$$__ $$ | $$_____/ | $$__ $$ \n");
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log(" | $$ \\ $$ | $$ | $$ \\ $$ \n");
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log(" | $$ | $$ | $$$$$ | $$ | $$ \n");
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log(" | $$ | $$ | $$__/ | $$ | $$ \n");
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log(" | $$/$$ $$ | $$ | $$ | $$ \n");
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log(" | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n");
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log(" \\____ $$$|__/|________/|__/|_______/|__/\n");
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log(" \\__/ \n");
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log("\n");
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}
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YOSYS_NAMESPACE_END
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#endif
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