mirror of
https://github.com/YosysHQ/yosys
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121 lines
4.2 KiB
Python
121 lines
4.2 KiB
Python
#!/usr/bin/env python3
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import os
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import numpy as np
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enable_upto = True
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enable_offset = True
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enable_hierarchy = True
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enable_logic = True
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def make_module(f, modname, width, subs):
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print("module %s (A, B, C, X, Y, Z);" % modname, file=f)
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inbits = list()
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outbits = list()
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for p in "ABC":
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offset = np.random.randint(10) if enable_offset else 0
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if enable_upto and np.random.randint(2):
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print(" input [%d:%d] %s;" % (offset, offset+width-1, p), file=f)
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else:
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print(" input [%d:%d] %s;" % (offset+width-1, offset, p), file=f)
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for i in range(offset, offset+width):
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inbits.append("%s[%d]" % (p, i))
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for p in "XYZ":
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offset = np.random.randint(10) if enable_offset else 0
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if enable_upto and np.random.randint(2):
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print(" output [%d:%d] %s;" % (offset, offset+width-1, p), file=f)
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else:
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print(" output [%d:%d] %s;" % (offset+width-1, offset, p), file=f)
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for i in range(offset, offset+width):
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outbits.append("%s[%d]" % (p, i))
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instidx = 0
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subcandidates = list(subs.keys())
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while len(outbits) > 0:
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submod = None
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if len(subcandidates):
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submod = np.random.choice(subcandidates)
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subcandidates.remove(submod)
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if submod is None or 3*subs[submod] >= len(outbits):
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for bit in outbits:
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if enable_logic:
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print(" assign %s = %s & ~%s;" % (bit, np.random.choice(inbits), np.random.choice(inbits)), file=f)
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else:
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print(" assign %s = %s;" % (bit, np.random.choice(inbits)), file=f)
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break
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instidx += 1
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print(" %s inst%d (" % (submod, instidx), file=f)
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for p in "ABC":
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print(" .%s({%s})," % (p, ",".join(np.random.choice(inbits, subs[submod]))), file=f)
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for p in "XYZ":
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bits = list(np.random.choice(outbits, subs[submod], False))
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for bit in bits:
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outbits.remove(bit)
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print(" .%s({%s})%s" % (p, ",".join(bits), "," if p != "Z" else ""), file=f)
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print(" );", file=f);
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print("endmodule", file=f)
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with open("test_top.v", "w") as f:
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if enable_hierarchy:
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make_module(f, "sub1", 2, {})
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make_module(f, "sub2", 3, {})
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make_module(f, "sub3", 4, {})
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make_module(f, "sub4", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
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make_module(f, "sub5", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
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make_module(f, "sub6", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
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make_module(f, "top", 32, {"sub4": 8, "sub5": 8, "sub6": 8})
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else:
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make_module(f, "top", 32, {})
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os.system("set -x; ../../yosys -p 'synth_xilinx -top top; write_edif -pvector par test_syn.edif' test_top.v")
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with open("test_syn.tcl", "w") as f:
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print("read_edif test_syn.edif", file=f)
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print("link_design", file=f)
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print("write_verilog -force test_syn.v", file=f)
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os.system("set -x; vivado -nojournal -nolog -mode batch -source test_syn.tcl")
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with open("test_tb.v", "w") as f:
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print("module tb;", file=f)
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print(" reg [31:0] A, B, C;", file=f)
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print(" wire [31:0] X, Y, Z;", file=f)
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print("", file=f)
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print(" top uut (", file=f)
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print(" .A(A),", file=f)
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print(" .B(B),", file=f)
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print(" .C(C),", file=f)
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print(" .X(X),", file=f)
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print(" .Y(Y),", file=f)
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print(" .Z(Z)", file=f)
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print(" );", file=f)
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print("", file=f)
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print(" initial begin", file=f)
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for i in range(100):
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print(" A = 32'h%08x;" % np.random.randint(2**32), file=f)
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print(" B = 32'h%08x;" % np.random.randint(2**32), file=f)
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print(" C = 32'h%08x;" % np.random.randint(2**32), file=f)
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print(" #10;", file=f)
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print(" $display(\"%x %x %x\", X, Y, Z);", file=f)
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print(" #10;", file=f)
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print(" $finish;", file=f)
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print(" end", file=f)
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print("endmodule", file=f)
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os.system("set -x; iverilog -o test_gold test_tb.v test_top.v")
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os.system("set -x; iverilog -o test_gate test_tb.v test_syn.v ../../techlibs/xilinx/cells_sim.v")
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os.system("set -x; ./test_gold > test_gold.out")
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os.system("set -x; ./test_gate > test_gate.out")
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os.system("set -x; md5sum test_gold.out test_gate.out")
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