Robert O'Callahan 8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.		2025-07-22 10:38:38 +00:00
..
.gitignore	Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.	2025-07-22 10:38:38 +00:00
alu.v	Add test cases for co-simulation	2022-02-02 13:22:44 +01:00
asserts.v
asserts.ys	tests: Run async2sync before sat and/or sim to handle $check cells	2024-02-01 16:14:11 +01:00
asserts_seq.v
asserts_seq.ys	tests: Run async2sync before sat and/or sim to handle $check cells	2024-02-01 16:14:11 +01:00
bug2595.ys	Remove references to ilang	2024-11-05 12:36:31 +13:00
clk2fflogic.ys
counters-repeat.v
counters-repeat.ys
counters.v
counters.ys
dff.ys
expose_dff.v
expose_dff.ys
grom.ys	bug fix and cleanups	2022-02-04 10:01:06 +01:00
grom_computer.v	Add test cases for co-simulation	2022-02-02 13:22:44 +01:00
grom_cpu.v	Proper example code	2022-03-14 15:39:11 +01:00
initval.v
initval.ys	tests: Run async2sync before sat and/or sim to handle $check cells	2024-02-01 16:14:11 +01:00
ram_memory.v	Proper example code	2022-03-14 15:39:11 +01:00
run-test.sh	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
share.v	share: Cleanup and additional testing	2025-04-15 12:34:46 +02:00
share.ys	share: Cleanup and additional testing	2025-04-15 12:34:46 +02:00
sim_counter.ys	Add test cases for co-simulation	2022-02-02 13:22:44 +01:00
sizebits.sv	Add support for $dimensions and $unpacked_dimensions	2024-02-11 11:26:52 -05:00
sizebits.ys	tests: Run async2sync before sat and/or sim to handle $check cells	2024-02-01 16:14:11 +01:00
splice.v
splice.ys	Added splice command	2014-02-07 20:30:56 +01:00