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yosys/tests/arch/intel_alm
History
Dan Ravensloft 5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
..
add_sub.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
adffs.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
counter.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
dffs.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
fsm.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
logic.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
lutram.ys intel_alm: direct LUTRAM cell instantiation 2020-05-07 21:03:13 +02:00
mux.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
quartus_ice.ys intel_alm: work around a Quartus ICE 2020-04-23 11:03:28 +02:00
run-test.sh synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
shifter.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
tribuf.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00