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https://github.com/YosysHQ/yosys
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102 lines
1.7 KiB
Text
102 lines
1.7 KiB
Text
read_verilog <<EOT
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module sub_3op(
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input [7:0] a, b, c,
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output [7:0] y
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);
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assign y = a - b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 1 t:$not
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select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module sub_mixed(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b - c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 1 t:$not
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select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module sub_all(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a - b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 3 t:$not
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select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module sub_5op(
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input [11:0] a, b, c, d, e,
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output [11:0] y
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);
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assign y = a - b + c - d + e;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 4 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 2 t:$not
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select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module sub_signed(
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input signed [7:0] a, b, c, d,
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output signed [9:0] y
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);
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assign y = a + b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 2 t:$not
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select -assert-none t:$sub
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design -reset
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read_verilog <<EOT
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module sub_double_neg(
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input [7:0] a, b, c,
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output [7:0] y
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);
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wire [7:0] ab = a - b;
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assign y = c - ab;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 1 t:$not
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select -assert-none t:$sub
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design -reset
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