mirror of
https://github.com/YosysHQ/yosys
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147 lines
2.3 KiB
Text
147 lines
2.3 KiB
Text
read_verilog <<EOT
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module add_1bit(
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input a, b, c,
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output [1:0] y
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);
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assign y = a + b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_1bit_wide(
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input a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_wide_out(
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input [7:0] a, b, c, d,
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output [31:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_mixed(
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input [7:0] a,
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input [3:0] b,
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input [15:0] c,
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input [7:0] d,
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output [15:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_signed(
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input signed [7:0] a, b, c, d,
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output signed [9:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_repeated(
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input [7:0] a,
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output [7:0] y
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);
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assign y = a + a + a + a;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_const(
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input [7:0] a, b, c,
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output [7:0] y
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);
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assign y = a + b + c + 8'd42;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_two(
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input [7:0] a, b, c, d, e, f, g, h,
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output [7:0] y1, y2
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);
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assign y1 = a + b + c + d;
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assign y2 = e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 4 t:$fa
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select -assert-count 2 t:$add
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design -reset
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read_verilog <<EOT
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module fir_4tap(
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input clk,
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input [15:0] x, c0, c1, c2, c3,
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output reg [31:0] y
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);
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reg [15:0] x1, x2, x3;
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always @(posedge clk) begin
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x1 <= x;
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x2 <= x1;
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x3 <= x2;
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end
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wire [31:0] sum = x*c0 + x1*c1 + x2*c2 + x3*c3;
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always @(posedge clk) y <= sum;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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