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https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
661fa5ff92
The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of the `$_XNOR_` cell.
131 lines
3.2 KiB
Text
131 lines
3.2 KiB
Text
# Single-bit $xnor
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read_verilog -noopt <<EOT
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module gold(input i, output o);
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assign o = 1'bx ~^ i;
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endmodule
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EOT
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select -assert-count 1 t:$xnor
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copy gold coarse
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copy gold fine
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copy gold coarse_keepdc
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copy gold fine_keepdc
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cd coarse
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opt_expr
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select -assert-none t:$xnor
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cd fine
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simplemap
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opt_expr
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select -assert-none c:t$_XNOR_
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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miter -equiv -flatten -make_assert -make_outputs coarse fine miter2
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sat -verify -prove-asserts -show-ports -enable_undef miter2
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cd coarse_keepdc
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opt_expr -keepdc
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select -assert-count 1 c:*
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cd fine_keepdc
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simplemap
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opt_expr -keepdc
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select -assert-count 1 t:$_XNOR_
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cd
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miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3
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sat -verify -prove-asserts -show-ports -enable_undef miter3
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miter -equiv -flatten -make_assert -make_outputs coarse_keepdc fine_keepdc miter4
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sat -verify -prove-asserts -show-ports -enable_undef miter4
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# Multi-bit $xnor
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design -reset
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read_verilog -noopt <<EOT
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module gold(input i, output [6:0] o);
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assign o = {1'bx, 1'b0, 1'b0, 1'b1, 1'bx, 1'b1, i} ~^ {7{i}};
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endmodule
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EOT
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select -assert-count 1 t:$xnor
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copy gold coarse
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copy gold fine
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copy gold coarse_keepdc
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copy gold fine_keepdc
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cd coarse
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opt_expr -fine
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select -assert-none t:$xnor
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cd fine
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simplemap
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opt_expr
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select -assert-none t:$_XNOR_
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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miter -equiv -flatten -make_assert -make_outputs coarse fine miter2
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sat -verify -prove-asserts -show-ports -enable_undef miter2
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cd coarse_keepdc
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opt_expr -keepdc -fine
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select -assert-count 1 t:$xnor
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cd fine_keepdc
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simplemap
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opt_expr -keepdc
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select -assert-count 0 c:$_XOR_
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cd
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miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3
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sat -verify -prove-asserts -show-ports -enable_undef miter3
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miter -equiv -flatten -make_assert -make_outputs coarse_keepdc fine_keepdc miter4
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sat -verify -prove-asserts -show-ports -enable_undef miter4
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# Single-bit $xnor extension
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design -reset
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read_verilog -noopt <<EOT
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module gold(input i, output [1:0] o, p, q);
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assign o = i ~^ i;
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assign p = 1'b0 ~^ i;
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assign q = 1'b1 ~^ i;
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endmodule
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EOT
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select -assert-count 3 t:$xnor
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copy gold coarse
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copy gold fine
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copy gold coarse_keepdc
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copy gold fine_keepdc
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cd coarse
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opt_expr -fine
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select -assert-none t:$xnor
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cd fine
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simplemap
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opt_expr
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select -assert-none t:$_XNOR_
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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miter -equiv -flatten -make_assert -make_outputs coarse fine miter2
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sat -verify -prove-asserts -show-ports -enable_undef miter2
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cd coarse_keepdc
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opt_expr -keepdc -fine
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select -assert-count 1 t:$xnor
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cd fine_keepdc
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simplemap
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opt_expr -keepdc
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select -assert-count 0 c:$_XNOR_
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cd
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miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3
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sat -verify -prove-asserts -show-ports -enable_undef miter3
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miter -equiv -flatten -make_assert -make_outputs coarse_keepdc fine_keepdc miter4
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sat -verify -prove-asserts -show-ports -enable_undef miter4
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