mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
517 lines
16 KiB
Python
517 lines
16 KiB
Python
import os
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import re
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import subprocess
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import itertools
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import random
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import argparse
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from pathlib import Path
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parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)
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parser.add_argument('-S', '--seed', type=int, help='seed for PRNG')
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parser.add_argument('-c', '--count', type=int, default=32, help='number of random patterns to test')
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parser.add_argument('-s', '--seq', action='store_true', help='run a sequential test')
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parser.add_argument('steps', nargs='*', help='steps to run')
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args = parser.parse_args()
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if args.seed is None:
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args.seed = random.randrange(1 << 32)
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print(f"PRNG seed: {args.seed}")
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random.seed(args.seed)
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steps = args.steps
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all_outputs = [
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"sim",
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"sim_xprop",
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"vsim_expr",
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"vsim_expr_xprop",
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"vsim_noexpr",
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"vsim_noexpr_xprop",
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"sat",
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"sat_xprop",
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]
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if not args.seq:
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all_outputs += ["opt_expr", "opt_expr_xprop"]
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if not steps:
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steps = ["clean", "prepare", "verify", *all_outputs, "compare"]
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if "clean" in steps:
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for output in all_outputs:
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try:
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os.unlink(f"{output}.out")
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except FileNotFoundError:
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pass
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def yosys(command):
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subprocess.check_call(["../../../yosys", "-Qp", command])
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def remove(file):
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try:
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os.unlink(file)
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except FileNotFoundError:
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pass
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def vcdextract(signals, on_change, file, output, limit=None):
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scope = []
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ids = {}
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prefix = []
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for line in file:
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line = prefix + line.split()
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if line[-1] != "$end":
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prefix = line
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continue
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prefix = []
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if not line:
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continue
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if line[0] == "$scope":
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scope.append(line[2].lstrip("\\"))
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elif line[0] == "$upscope":
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scope.pop()
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elif line[0] == "$var":
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ids[".".join(scope + [line[4].lstrip("\\")])] = line[3]
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elif line[0] == "$enddefinitions":
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break
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elif line[0] in ["$version", "$date", "$comment"]:
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continue
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else:
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raise RuntimeError(f"unexpected input in vcd {line}")
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dump_pos = {}
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for i, sig in enumerate(signals + on_change):
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dump_pos[ids[sig]] = i
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values = [None] * len(signals + on_change)
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last_values = []
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counter = 0
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for line in file:
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if line.startswith("#"):
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if None in values:
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continue
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if values != last_values:
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last_values = list(values)
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if limit is None or counter < limit:
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print(*values[:len(signals)], file=output)
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counter += 1
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continue
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if line.startswith("b"):
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value, id = line[1:].split()
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else:
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value, id = line[:1], line[1:]
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pos = dump_pos.get(id)
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if pos is None:
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continue
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values[pos] = value
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if values != last_values:
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if limit is None or counter < limit:
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print(*values[:len(signals)], file=output)
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share = Path(__file__).parent / ".." / ".." / "share"
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simlibs = [str(share / "simlib.v"), str(share / "simcells.v")]
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if "prepare" in steps:
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yosys(
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"""
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read_verilog -icells uut.v
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hierarchy -top uut; proc -noopt
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write_rtlil uut.il
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dump -o ports.list uut/x:*
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"""
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)
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inputs = []
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outputs = []
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with open("ports.list") as ports_file:
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for line in ports_file:
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line = line.split()
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if not line or line[0] != "wire":
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continue
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line = line[1:]
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width = 1
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if line[0] == "width":
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width = int(line[1])
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line = line[2:]
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direction, seq, name = line
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assert name.startswith("\\")
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name = name[1:]
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seq = int(seq)
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if direction == "input":
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inputs.append((seq, name, width))
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else:
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outputs.append((seq, name, width))
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inputs.sort()
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outputs.sort()
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input_width = sum(width for seq, name, width in inputs)
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output_width = sum(width for seq, name, width in outputs)
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if "prepare" in steps:
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if args.seq:
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patterns = [''.join(random.choices('01x', k=input_width)) for i in range(args.count)]
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else:
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if 3**input_width <= args.count * 2:
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patterns = ["".join(bits) for bits in itertools.product(*["01x"] * input_width)]
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else:
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patterns = set()
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for bit in '01x':
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patterns.add(bit * input_width)
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for bits in itertools.combinations('01x', 2):
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for bit1, bit2 in itertools.permutations(bits):
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for i in range(input_width):
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pattern = [bit1] * input_width
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pattern[i] = bit2
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patterns.add(''.join(pattern))
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for i, j in itertools.combinations(range(input_width), 2):
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pattern = [bit1] * input_width
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pattern[i] = bit2
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pattern[j] = bit2
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patterns.add(''.join(pattern))
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for bit1, bit2, bit3 in itertools.permutations('01x'):
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for i, j in itertools.combinations(range(input_width), 2):
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pattern = [bit1] * input_width
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pattern[i] = bit2
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pattern[j] = bit3
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patterns.add(''.join(pattern))
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if len(patterns) > args.count // 2:
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patterns = sorted(patterns)
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random.shuffle(patterns)
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patterns = set(patterns[:args.count // 2])
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while len(patterns) < args.count:
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pattern = ''.join(random.choices('01x', k=input_width))
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patterns.add(pattern)
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patterns = sorted(patterns)
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with open("patterns.list", "w") as f:
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for pattern in patterns:
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print(pattern, file=f)
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else:
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with open("patterns.list") as f:
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patterns = [pattern.strip() for pattern in f]
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if "prepare" in steps:
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with open("wrapper.v", "w") as wrapper_file:
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print(
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"module wrapper("
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f"input [{input_width-1}:0] A, "
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f"output [{output_width-1}:0] Y);",
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file=wrapper_file,
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)
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connections = []
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pos = 0
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for seq, name, width in inputs:
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connections.append(f".{name}(A[{pos+width-1}:{pos}])")
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pos += width
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pos = 0
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for seq, name, width in outputs:
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connections.append(f".{name}(Y[{pos+width-1}:{pos}])")
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pos += width
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print(f"uut uut({', '.join(connections)});", file=wrapper_file)
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print("endmodule", file=wrapper_file)
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yosys(
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"""
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read_rtlil uut.il
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read_verilog wrapper.v
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hierarchy -top wrapper; proc -noopt
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flatten; clean;
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rename wrapper uut
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write_rtlil wrapped.il
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"""
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)
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try:
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yosys(
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"""
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read_rtlil wrapped.il
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dffunmap
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xprop -required
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check -assert
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write_rtlil wrapped_xprop.il
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"""
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)
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except subprocess.CalledProcessError:
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remove("wrapped_xprop.il")
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with open("verilog_sim_tb.v", "w") as tb_file:
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print("module top();", file=tb_file)
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print(f"reg gclk;", file=tb_file)
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print(f"reg [{input_width-1}:0] A;", file=tb_file)
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print(f"wire [{output_width-1}:0] Y;", file=tb_file)
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print(f"uut uut(.A(A), .Y(Y));", file=tb_file)
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print("initial begin", file=tb_file)
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for pattern in patterns:
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# A[0] might be the clock which requires special sequencing
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print(
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f' #0; gclk = 1; #0; A[0] = 1\'b{pattern[-1]}; #0; A = {input_width}\'b{pattern}; #5; gclk = 0; $display("%b %b", A, Y); #5',
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file=tb_file,
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)
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print(" $finish(0);", file=tb_file)
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print("end", file=tb_file)
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print("endmodule", file=tb_file)
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with open("synth_tb.v", "w") as tb_file:
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print("module top(input clk);", file=tb_file)
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print(f"reg [{len(patterns).bit_length() - 1}:0] counter = 0;", file=tb_file)
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print(f"reg [{input_width-1}:0] A;", file=tb_file)
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print(f"(* gclk *) reg gclk;", file=tb_file)
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print(f"wire [{output_width-1}:0] Y;", file=tb_file)
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print(f"uut uut(.A(A), .Y(Y));", file=tb_file)
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print(f"always @(posedge gclk) counter <= counter + 1;", file=tb_file)
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print(f"always @* case (counter)", file=tb_file)
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for i, pattern in enumerate(patterns):
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print(f" {i:7} : A = {input_width}'b{pattern};", file=tb_file)
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print(f" default : A = {input_width}'b{'x' * input_width};", file=tb_file)
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print(f"endcase", file=tb_file)
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print("endmodule", file=tb_file)
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with open("const_tb.v", "w") as tb_file:
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print("module top();", file=tb_file)
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for i, pattern in enumerate(patterns):
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print(
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f"(* keep *) wire [{output_width-1}:0] Y_{i}; "
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f"uut uut_{i}(.A({input_width}'b{pattern}), .Y(Y_{i}));",
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file=tb_file,
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)
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print("endmodule", file=tb_file)
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if "verify" in steps:
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try:
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seq_args = " -tempinduct -set-init-undef" if args.seq else ""
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yosys(
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f"""
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read_rtlil wrapped.il
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copy uut gold
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rename uut gate
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design -push-copy
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dffunmap
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xprop -formal -split-inputs -required -debug-asserts gate
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clk2fflogic
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sat{seq_args} -enable_undef -set-def-inputs -prove-asserts -verify -show-all gate
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design -pop
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dffunmap
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xprop -required -assume-encoding gate
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miter -equiv -make_assert -flatten gold gate miter
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clk2fflogic
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sat{seq_args} -enable_undef -set-assumes -prove-asserts -verify -show-all miter
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"""
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)
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with open("verified", "w") as f:
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pass
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except subprocess.CalledProcessError:
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remove("verified")
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for mode in ["", "_xprop"]:
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if not Path(f"wrapped{mode}.il").is_file():
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for expr in [f"expr{mode}", f"noexpr{mode}"]:
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remove(f"vsim_{expr}.out")
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continue
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if "prepare" in steps:
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yosys(
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f"""
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read_rtlil wrapped{mode}.il
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chformal -remove
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dffunmap
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write_verilog -noexpr vsim_noexpr{mode}.v
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write_verilog -noparallelcase vsim_expr{mode}.v
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"""
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)
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for expr in [f"expr{mode}", f"noexpr{mode}"]:
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if f"vsim_{expr}" in steps:
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subprocess.check_call(
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[
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"iverilog",
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"-DSIMLIB_FF",
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"-DSIMLIB_GLOBAL_CLOCK=top.gclk",
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f"-DDUMPFILE=\"vsim_{expr}.vcd\"",
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"-o",
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f"vsim_{expr}",
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"verilog_sim_tb.v",
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f"vsim_{expr}.v",
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*simlibs,
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]
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)
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with open(f"vsim_{expr}.out", "w") as f:
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subprocess.check_call(["vvp", f"./vsim_{expr}"], stdout=f)
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for mode in ["", "_xprop"]:
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if f"sim{mode}" not in steps:
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continue
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if not Path(f"wrapped{mode}.il").is_file():
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remove(f"sim{mode}.out")
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continue
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yosys(
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f"""
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read_verilog synth_tb.v
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read_rtlil wrapped{mode}.il
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hierarchy -top top; proc -noopt
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dffunmap
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sim -clock clk -n {len(patterns) // 2} -vcd sim{mode}.vcd top
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"""
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)
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with open(f"sim{mode}.vcd") as fin, open(f"sim{mode}.out", "w") as fout:
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vcdextract(["top.A", "top.Y"], ["top.counter"], fin, fout, len(patterns))
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for mode in ["", "_xprop"]:
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if f"sat{mode}" not in steps:
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continue
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if not Path(f"wrapped{mode}.il").is_file():
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remove(f"sat{mode}.out")
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continue
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chunk_size = len(patterns) if args.seq else 32
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last_progress = 0
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with open(f"sat{mode}.ys", "w") as ys:
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for chunk_start in range(0, len(patterns), chunk_size):
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chunk = patterns[chunk_start : chunk_start + chunk_size]
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progress = (10 * chunk_start) // len(patterns)
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if progress > last_progress:
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print(f"log sat {progress}0%", file=ys)
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last_progress = progress
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append = "-a" if chunk_start else "-o"
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print(
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end=f"tee -q {append} sat{mode}.log sat -set-init-undef -seq {len(chunk)}"
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" -show A -show Y -dump_vcd sat.vcd -enable_undef",
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file=ys,
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)
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for i, pattern in enumerate(chunk, 1):
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ad = pattern.replace("x", "0")
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ax = pattern.replace("1", "0").replace("x", "1")
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print(end=f" -set-at {i} A {input_width}'b{pattern}", file=ys)
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print(file=ys)
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print(f"log sat 100%", file=ys)
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try:
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yosys(
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f"""
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read_rtlil wrapped{mode}.il
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clk2fflogic
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script sat{mode}.ys
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"""
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)
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except subprocess.CalledProcessError:
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remove(f"sat{mode}.out")
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else:
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sig_re = re.compile(
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r" *[0-9]+ +\\([AY]) +(?:--|[0-9]+) +(?:--|[0-9a-f]+) +([01x]+)"
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)
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current_input = None
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with open(f"sat{mode}.log") as logfile, open(f"sat{mode}.out", "w") as outfile:
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for line in logfile:
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match = sig_re.match(line)
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if match:
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if match[1] == "A":
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current_input = match[2]
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else:
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print(current_input, match[2], file=outfile)
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for mode in ["", "_xprop"]:
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if f"opt_expr{mode}" not in steps:
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continue
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if not Path(f"wrapped{mode}.il").is_file():
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remove(f"opt_expr{mode}.out")
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continue
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yosys(
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f"""
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read_verilog const_tb.v
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read_rtlil wrapped{mode}.il
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hierarchy -top top; proc -noopt
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flatten
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opt_expr -keepdc; clean
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dump -o opt_expr{mode}.list */\Y_*
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"""
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)
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values = []
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connect_re = re.compile(r" *connect +\\Y_([0-9]+) +[0-9]+'([01x]+)$")
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with open(f"opt_expr{mode}.list") as connections:
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for line in connections:
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match = connect_re.match(line)
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if match:
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seq = int(match[1])
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data = match[2]
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if len(data) < output_width:
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data = data * output_width
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values.append((seq, data))
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values.sort()
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with open(f"opt_expr{mode}.out", "w") as outfile:
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for seq, data in values:
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print(patterns[seq], data, file=outfile)
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if "compare" in steps:
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groups = {}
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missing = []
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for output in all_outputs:
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try:
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with open(f"{output}.out") as f:
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groups.setdefault(f.read(), []).append(output)
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except FileNotFoundError:
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missing.append(output)
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verified = Path(f"verified").is_file()
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with open("status", "w") as status:
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name = Path('.').absolute().name
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status_list = []
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if len(groups) > 1:
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status_list.append("mismatch")
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if not verified:
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status_list.append("failed-verify")
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if missing:
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status_list.append("missing")
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if not status_list:
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status_list.append("ok")
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print(f"{name}: {', '.join(status_list)}", file=status)
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if len(groups) > 1:
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print("output differences:", file=status)
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for group in groups.values():
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print(" -", *group, file=status)
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if missing:
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print("missing:", file=status)
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print(" -", *missing, file=status)
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with open("status") as status:
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print(end=status.read())
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