mirror of
https://github.com/YosysHQ/yosys
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2a68eee5f1
Use `$finish(0)` to silently exit even when using recent iverlog versions. Run `write_verilog -noexpr` before `write_verilog` as the latter can modify the design. This also enables checking the tests results, as xprop should be in a state where the existing tests pass.
287 lines
10 KiB
Python
287 lines
10 KiB
Python
import os
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import re
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import sys
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import random
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import argparse
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parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)
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parser.add_argument('-S', '--seed', type=int, help='seed for PRNG')
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parser.add_argument('-m', '--more', action='store_true', help='run more tests')
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parser.add_argument('-c', '--count', type=int, default=32, help='number of random patterns to test')
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parser.add_argument('-f', '--filter', default='', help='regular expression to filter tests to generate')
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args = parser.parse_args()
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if args.seed is None:
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args.seed = random.randrange(1 << 32)
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print(f"xprop PRNG seed: {args.seed}")
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makefile = open("run-test.mk", "w")
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def add_test(name, src, seq=False):
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if not re.search(args.filter, name):
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return
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workdir = f"xprop_{name}"
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os.makedirs(workdir, exist_ok=True)
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with open(f"{workdir}/uut.v", "w") as uut:
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print(src, file=uut)
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print(f"all: {workdir}", file=makefile)
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print(f".PHONY: {workdir}", file=makefile)
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print(f"{workdir}:", file=makefile)
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seq_arg = " -s" if seq else ""
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print(
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f"\t@cd {workdir} && python3 -u ../test.py -S {args.seed} -c {args.count}{seq_arg} > test.log 2>&1 || echo {workdir}: failed > status\n"
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f"\t@cat {workdir}/status\n"
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f"\t@grep '^.*: ok' {workdir}/status\n"
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,
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file=makefile,
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)
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def cell_test(name, cell, inputs, outputs, params, initial={}, defclock=False, seq=False):
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ports = []
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port_conns = []
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for inport, width in inputs.items():
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ports.append(f"input [{width-1}:0] {inport}")
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if defclock and inport in ["C", "CLK"]:
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port_conns.append(f".{inport}({inport} !== 0)")
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else:
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port_conns.append(f".{inport}({inport})")
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for outport, width in outputs.items():
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reg = " reg" if outport in initial else ""
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ports.append(f"output{reg} [{width-1}:0] {outport}")
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port_conns.append(f".{outport}({outport})")
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param_defs = []
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for param, value in params.items():
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param_defs.append(f".{param}({value})")
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initials = []
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# for port, value in initial.items():
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# initials.append(f"initial {port} = {value};\n")
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add_test(name,
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f"module uut({', '.join(ports)});\n"
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f"\\${cell} #({', '.join(param_defs)}) cell ({', '.join(port_conns)});\n"
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f"{''.join(initials)}"
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"endmodule",
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seq=seq,
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)
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def unary_test(cell, width, signed, out_width):
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add_test(
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f"{cell}_{width}{'us'[signed]}_{out_width}",
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f"module uut(input [{width-1}:0] A, output [{out_width}-1:0] Y);\n"
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f"\\${cell} #(.A_WIDTH({width}), .A_SIGNED({int(signed)}), .Y_WIDTH({out_width}))"
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" cell (.A(A), .Y(Y));\n"
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"endmodule",
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)
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def binary_test(cell, a_width, b_width, signed, out_width):
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add_test(
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f"{cell}_{a_width}{'us'[signed]}{b_width}_{out_width}",
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f"module uut(input [{a_width-1}:0] A, input [{b_width-1}:0] B, output [{out_width}-1:0] Y);\n"
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f"\\${cell} #(.A_WIDTH({a_width}), .A_SIGNED({int(signed)}), .B_WIDTH({b_width}), .B_SIGNED({int(signed)}), .Y_WIDTH({out_width}))"
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" cell (.A(A), .B(B), .Y(Y));\n"
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"endmodule",
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)
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def shift_test(cell, a_width, b_width, a_signed, b_signed, out_width):
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add_test(
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f"{cell}_{a_width}{'us'[a_signed]}{b_width}{'us'[b_signed]}_{out_width}",
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f"module uut(input [{a_width-1}:0] A, input [{b_width-1}:0] B, output [{out_width}-1:0] Y);\n"
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f"\\${cell} #(.A_WIDTH({a_width}), .A_SIGNED({int(a_signed)}), .B_WIDTH({b_width}), .B_SIGNED({int(b_signed)}), .Y_WIDTH({out_width}))"
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" cell (.A(A), .B(B), .Y(Y));\n"
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"endmodule",
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)
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def mux_test(width):
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cell_test(f"mux_{width}", 'mux', {"A": width, "B": width, "S": 1}, {"Y": width}, {"WIDTH": width})
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def bmux_test(width, s_width):
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cell_test(f"bmux_{width}_{s_width}", 'bmux', {"A": width << s_width, "S": s_width}, {"Y": width}, {"WIDTH": width, "S_WIDTH": s_width})
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def demux_test(width, s_width):
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cell_test(f"demux_{width}_{s_width}", 'demux', {"A": width, "S": s_width}, {"Y": width << s_width}, {"WIDTH": width, "S_WIDTH": s_width})
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def pmux_test(width, s_width):
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cell_test(f"pmux_{width}_{s_width}", 'pmux', {"A": width, "B": width * s_width, "S": s_width}, {"Y": width}, {"WIDTH": width, "S_WIDTH": s_width})
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def bwmux_test(width):
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cell_test(f"bwmux_{width}", 'bwmux', {"A": width, "B": width, "S": width}, {"Y": width}, {"WIDTH": width})
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def bweqx_test(width):
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cell_test(f"bweqx_{width}", 'bweqx', {"A": width, "B": width}, {"Y": width}, {"WIDTH": width})
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def ff_test(width):
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cell_test(f"ff_{width}", 'ff', {"D": width}, {"Q": width}, {"WIDTH": width}, seq=True)
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def dff_test(width, pol, defclock):
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cell_test(f"dff_{width}{'np'[pol]}{'xd'[defclock]}", 'dff', {"CLK": 1, "D": width}, {"Q": width}, {"WIDTH": width, "CLK_POLARITY": int(pol)}, defclock=defclock, seq=True)
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def dffe_test(width, pol, enpol, defclock):
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cell_test(f"dffe_{width}{'np'[pol]}{'np'[enpol]}{'xd'[defclock]}", 'dffe', {"CLK": 1, "EN": 1, "D": width}, {"Q": width}, {"WIDTH": width, "CLK_POLARITY": int(pol), "EN_POLARITY": int(enpol)}, defclock=defclock, seq=True)
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print(".PHONY: all", file=makefile)
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print("all:\n\t@echo done\n", file=makefile)
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for cell in ["not", "pos", "neg"]:
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if args.more:
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unary_test(cell, 1, False, 1)
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unary_test(cell, 3, False, 3)
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unary_test(cell, 3, True, 3)
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unary_test(cell, 3, True, 1)
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unary_test(cell, 3, False, 5)
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unary_test(cell, 3, True, 5)
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for cell in ["and", "or", "xor", "xnor"]:
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binary_test(cell, 1, 1, False, 1)
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binary_test(cell, 1, 1, True, 2)
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binary_test(cell, 2, 2, False, 2)
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if args.more:
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binary_test(cell, 2, 2, False, 1)
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binary_test(cell, 2, 1, False, 2)
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binary_test(cell, 2, 1, False, 1)
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# [, "pow"] are not implemented yet
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for cell in ["add", "sub", "mul", "div", "mod", "divfloor", "modfloor"]:
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if args.more:
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binary_test(cell, 1, 1, False, 1)
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binary_test(cell, 1, 1, False, 2)
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binary_test(cell, 3, 3, False, 1)
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binary_test(cell, 3, 3, False, 3)
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binary_test(cell, 3, 3, False, 6)
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binary_test(cell, 3, 3, True, 1)
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binary_test(cell, 3, 3, True, 3)
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binary_test(cell, 3, 3, True, 6)
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binary_test(cell, 5, 3, False, 3)
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binary_test(cell, 5, 3, True, 3)
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for cell in ["lt", "le", "eq", "ne", "eqx", "nex", "ge", "gt"]:
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if args.more:
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binary_test(cell, 1, 1, False, 1)
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binary_test(cell, 1, 1, False, 2)
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binary_test(cell, 3, 3, False, 1)
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binary_test(cell, 3, 3, False, 2)
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binary_test(cell, 3, 3, True, 1)
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binary_test(cell, 3, 3, True, 2)
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binary_test(cell, 5, 3, False, 1)
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binary_test(cell, 5, 3, True, 1)
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binary_test(cell, 5, 3, False, 2)
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binary_test(cell, 5, 3, True, 2)
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for cell in ["reduce_and", "reduce_or", "reduce_xor", "reduce_xnor"]:
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if args.more:
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unary_test(cell, 1, False, 1)
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unary_test(cell, 3, False, 1)
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unary_test(cell, 3, True, 1)
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unary_test(cell, 3, False, 3)
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unary_test(cell, 3, True, 3)
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for cell in ["reduce_bool", "logic_not"]:
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unary_test(cell, 1, False, 1)
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unary_test(cell, 3, False, 3)
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unary_test(cell, 3, True, 3)
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unary_test(cell, 3, True, 1)
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for cell in ["logic_and", "logic_or"]:
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binary_test(cell, 1, 1, False, 1)
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binary_test(cell, 3, 3, False, 3)
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binary_test(cell, 3, 3, True, 3)
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binary_test(cell, 3, 3, True, 1)
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for cell in ["shl", "shr", "sshl", "sshr", "shift"]:
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if args.more:
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shift_test(cell, 2, 1, False, False, 2)
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shift_test(cell, 2, 1, True, False, 2)
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shift_test(cell, 2, 1, False, False, 4)
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shift_test(cell, 2, 1, True, False, 4)
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shift_test(cell, 4, 2, False, False, 4)
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shift_test(cell, 4, 2, True, False, 4)
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shift_test(cell, 4, 2, False, False, 8)
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shift_test(cell, 4, 2, True, False, 8)
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shift_test(cell, 4, 3, False, False, 3)
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shift_test(cell, 4, 3, True, False, 3)
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for cell in ["shift"]:
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if args.more:
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shift_test(cell, 2, 1, False, True, 2)
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shift_test(cell, 2, 1, True, True, 2)
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shift_test(cell, 2, 1, False, True, 4)
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shift_test(cell, 2, 1, True, True, 4)
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shift_test(cell, 4, 2, False, True, 4)
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shift_test(cell, 4, 2, True, True, 4)
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shift_test(cell, 4, 2, False, True, 8)
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shift_test(cell, 4, 2, True, True, 8)
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shift_test(cell, 4, 3, False, True, 3)
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shift_test(cell, 4, 3, True, True, 3)
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for cell in ["shiftx"]:
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if args.more:
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shift_test(cell, 2, 1, False, True, 2)
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shift_test(cell, 2, 1, False, True, 4)
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shift_test(cell, 4, 2, False, True, 4)
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shift_test(cell, 4, 2, False, True, 8)
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shift_test(cell, 4, 3, False, True, 3)
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mux_test(1)
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mux_test(3)
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bmux_test(1, 2)
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bmux_test(2, 2)
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bmux_test(3, 1)
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demux_test(1, 2)
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demux_test(2, 2)
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demux_test(3, 1)
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pmux_test(1, 4)
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pmux_test(2, 2)
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pmux_test(3, 1)
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pmux_test(4, 4)
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bwmux_test(1)
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bwmux_test(3)
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bweqx_test(1)
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bweqx_test(3)
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ff_test(1)
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ff_test(3)
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dff_test(1, True, True)
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dff_test(1, False, True)
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dff_test(3, True, True)
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dff_test(3, False, True)
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# dff_test(1, True, False) # TODO support x clocks
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# dff_test(1, False, False) # TODO support x clocks
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# dff_test(3, True, False) # TODO support x clocks
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# dff_test(3, False, False) # TODO support x clocks
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dffe_test(1, True, False, True)
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dffe_test(1, False, False, True)
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dffe_test(3, True, False, True)
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dffe_test(3, False, False, True)
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dffe_test(1, True, True, True)
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dffe_test(1, False, True, True)
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dffe_test(3, True, True, True)
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dffe_test(3, False, True, True)
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# TODO "shift", "shiftx"
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# TODO "fa", "lcu", "alu", "macc", "lut", "sop"
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# TODO "slice", "concat"
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# TODO "tribuf", "specify2", "specify3", "specrule"
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# TODO "assert", "assume", "live", "fair", "cover", "initstate", "anyconst", "anyseq", "anyinit", "allconst", "allseq", "equiv",
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# TODO "bweqx", "bwmux"
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# TODO "sr", "ff", "dff", "dffe", "dffsr", "sffsre", "adff", "aldff", "sdff", "adffe", "aldffe", "sdffe", "sdffce", "dlatch", "adlatch", "dlatchsr"
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# TODO "fsm"
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# TODO "memrd", "memrd_v2", "memwr", "memwr_v2", "meminit", "meminit_v2", "mem", "mem_v2"
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