mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
88be728353
- Rewrite all Python features to use the pybind11 library instead of boost::python. Unlike boost::python, pybind11 is a header-only library that is just included by Pyosys code, saving a lot of compile time on wheels. - Factor out as much "translation" code from the generator into proper C++ files - Fix running the embedded interpreter not supporting "from pyosys import libyosys as ys" like wheels - Move Python-related elements to `pyosys` directory at the root of the repo - Slight shift in bridging semantics: - Containers are declared as "opaque types" and are passed by reference to Python - many methods have been implemented to make them feel right at home without the overhead/ambiguity of copying to Python and then copying back after mutation - Monitor/Pass use "trampoline" pattern to support virual methods overridable in Python: virtual methods no longer require `py_` prefix - Create really short test set for pyosys that just exercises basic functionality
45 lines
2.9 KiB
Python
45 lines
2.9 KiB
Python
from pyosys import libyosys as ys
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from pathlib import Path
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__file_dir__ = Path(__file__).absolute().parent
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d = ys.Design()
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ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
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ys.run_pass("hierarchy -top spm", d)
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name_by_tv_location = []
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name_by_au_location = []
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# test both dictionary mapping and equiv operators working fine
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module = None
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print(d.modules_)
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for idstr, module_obj in d.modules_.items():
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if idstr != ys.IdString("\\spm"):
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continue
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if idstr.str() != "\\spm":
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continue
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module = module_obj
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break
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assert module == d.top_module(), "top module search failed"
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for name in module.ports:
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wire = module.wires_[name]
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name_str = name.str()
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if name_str.endswith(".d"): # single reg output, in au
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name_by_au_location.append(name_str[1:-2])
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elif name_str.endswith(".q"): # single reg input, in tv
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name_by_tv_location.append(name_str[1:-2])
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else: # port/boundary scan
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frm = wire.start_offset + wire.width
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to = wire.start_offset
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for i in range(frm - 1, to - 1, -1):
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bit_name = name_str[1:] + f"\\[{i}\\]"
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if wire.port_input:
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name_by_tv_location.append(bit_name)
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elif wire.port_output:
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name_by_au_location.append(bit_name)
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assert name_by_tv_location == ['x\\[0\\]', 'a\\[31\\]', 'a\\[30\\]', 'a\\[29\\]', 'a\\[28\\]', 'a\\[27\\]', 'a\\[26\\]', 'a\\[25\\]', 'a\\[24\\]', 'a\\[23\\]', 'a\\[22\\]', 'a\\[21\\]', 'a\\[20\\]', 'a\\[19\\]', 'a\\[18\\]', 'a\\[17\\]', 'a\\[16\\]', 'a\\[15\\]', 'a\\[14\\]', 'a\\[13\\]', 'a\\[12\\]', 'a\\[11\\]', 'a\\[10\\]', 'a\\[9\\]', 'a\\[8\\]', 'a\\[7\\]', 'a\\[6\\]', 'a\\[5\\]', 'a\\[4\\]', 'a\\[3\\]', 'a\\[2\\]', 'a\\[1\\]', 'a\\[0\\]', '_315_', '_314_', '_313_', '_312_', '_311_', '_310_', '_309_', '_308_', '_307_', '_306_', '_305_', '_304_', '_303_', '_302_', '_301_', '_300_', '_299_', '_298_', '_297_', '_296_', '_295_', '_294_', '_293_', '_292_', '_291_', '_290_', '_289_', '_288_', '_287_', '_286_', '_285_', '_284_', '_283_', '_282_', '_281_', '_280_', '_279_', '_278_', '_277_', '_276_', '_275_', '_274_', '_273_', '_272_', '_271_', '_270_', '_269_', '_268_', '_267_', '_266_', '_265_', '_264_', '_263_', '_262_', '_261_', '_260_', '_259_', '_258_', '_257_', '_256_', '_255_', '_254_', '_253_', '_252_'], "failed to extract test vector register locations"
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assert name_by_au_location == ['y\\[0\\]', '_315_', '_314_', '_313_', '_312_', '_311_', '_310_', '_309_', '_308_', '_307_', '_306_', '_305_', '_304_', '_303_', '_302_', '_301_', '_300_', '_299_', '_298_', '_297_', '_296_', '_295_', '_294_', '_293_', '_292_', '_291_', '_290_', '_289_', '_288_', '_287_', '_286_', '_285_', '_284_', '_283_', '_282_', '_281_', '_280_', '_279_', '_278_', '_277_', '_276_', '_275_', '_274_', '_273_', '_272_', '_271_', '_270_', '_269_', '_268_', '_267_', '_266_', '_265_', '_264_', '_263_', '_262_', '_261_', '_260_', '_259_', '_258_', '_257_', '_256_', '_255_', '_254_', '_253_', '_252_'], "failed to extract golden output register locations"
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print("ok!")
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