mirror of
https://github.com/YosysHQ/yosys
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209 lines
3.2 KiB
Text
209 lines
3.2 KiB
Text
# Bad case: independent write ports.
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read_verilog << EOT
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module top(
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input [3:0] wa1, wa2, ra, wd1, wd2,
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input clk, we1, we2,
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output [3:0] rd);
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reg [3:0] mem[0:15];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1)
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mem[wa1] <= wd1;
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if (we2)
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mem[wa2] <= wd2;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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memory -nomap
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0100 %i
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design -reset
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# Good case: write ports with definitely different addresses.
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read_verilog << EOT
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module top(
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input [3:0] wa, ra, wd1, wd2,
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input clk, we1, we2,
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output [3:0] rd);
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reg [3:0] mem[0:15];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1)
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mem[wa] <= wd1;
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if (we2)
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mem[wa ^ 1] <= wd2;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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memory -nomap
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i
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design -reset
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# Bad case 2: the above, but broken.
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read_verilog << EOT
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module top(
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input [3:0] wa, ra, wd1, wd2,
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input clk, we1, we2,
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output [3:0] rd);
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reg [3:0] mem[0:15];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1)
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mem[wa] <= wd1;
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if (we2)
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mem[wa | 1] <= wd2;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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memory -nomap
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0100 %i
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design -reset
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# Good case 2: write ports with disjoint bit enables.
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read_verilog << EOT
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module top(
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input [3:0] wa1, wa2, ra,
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input [1:0] wd1, wd2,
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input clk, we1, we2,
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output [3:0] rd);
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reg [3:0] mem[0:15];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1)
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mem[wa1][1:0] <= wd1;
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if (we2)
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mem[wa2][3:2] <= wd2;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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memory -nomap
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i
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design -reset
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# Good case 3: write ports with soft priority logic already
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read_verilog << EOT
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module top(
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input [3:0] wa1, wa2, ra, wd1, wd2,
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input clk, we1, we2,
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output [3:0] rd);
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reg [3:0] mem[0:15];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1)
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mem[wa1] <= wd1;
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if (we2 && wa1 != wa2)
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mem[wa2] <= wd2;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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memory -nomap
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i
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design -reset
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# Good case 4: two wide write ports
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read_verilog << EOT
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module top(
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input [5:0] wa1, wa2,
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input [7:0] ra,
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input [31:0] wd1, wd2,
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input clk, we1, we2,
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output [7:0] rd);
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reg [7:0] mem[0:255];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1) begin
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mem[{wa1, 2'b00}] <= wd1[7:0];
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mem[{wa1, 2'b01}] <= wd1[15:8];
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mem[{wa1, 2'b10}] <= wd1[23:16];
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mem[{wa1, 2'b11}] <= wd1[31:24];
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end
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if (we2) begin
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mem[{wa2, 2'b00}] <= wd2[7:0];
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mem[{wa2, 2'b01}] <= wd2[15:8];
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mem[{wa2, 2'b10}] <= wd2[23:16];
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mem[{wa2, 2'b11}] <= wd2[31:24];
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end
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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opt_mem_priority
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memory_collect
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=64'h0804020100000000 %i
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memory_share
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=64'h0f0f0f0f00000000 %i
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select -assert-count 1 t:$mem_v2 r:WR_WIDE_CONTINUATION=8'hee %i
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