mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 11:42:30 +00:00 
			
		
		
		
	
		
			
				
	
	
		
			23 lines
		
	
	
	
		
			306 B
		
	
	
	
		
			Text
		
	
	
	
	
	
			
		
		
	
	
			23 lines
		
	
	
	
		
			306 B
		
	
	
	
		
			Text
		
	
	
	
	
	
| read_rtlil << EOF
 | |
| 
 | |
| module \top
 | |
| 
 | |
|   wire width 4 input 1 \A
 | |
| 
 | |
|   wire output 2 \Y
 | |
| 
 | |
|   cell $lut \lut
 | |
|     parameter \LUT 16'1111110011000000
 | |
|     parameter \WIDTH 4
 | |
|     connect \A \A
 | |
|     connect \Y \Y
 | |
|   end
 | |
| end
 | |
| 
 | |
| EOF
 | |
| 
 | |
| equiv_opt -assert opt_lut_ins
 | |
| 
 | |
| design -load postopt
 | |
| 
 | |
| select -assert-count 1 t:$lut r:WIDTH=3 %i
 |