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160 lines
4.1 KiB
Text
160 lines
4.1 KiB
Text
# Testing edge cases where ports are signed/have different widths/shift amounts
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# greater than the size
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read_verilog <<EOT
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module top (
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input wire [3:0] in_u,
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input wire signed [3:0] in_s,
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output wire [7:0] shl_uu,
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output wire signed [7:0] shl_us,
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output wire [7:0] shl_su,
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output wire signed [7:0] shl_ss,
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output wire [7:0] shr_uu,
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output wire signed [7:0] shr_us,
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output wire [7:0] shr_su,
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output wire signed [7:0] shr_ss,
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output wire [7:0] sshl_uu,
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output wire signed [7:0] sshl_us,
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output wire [7:0] sshl_su,
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output wire signed [7:0] sshl_ss,
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output wire [7:0] sshr_uu,
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output wire signed [7:0] sshr_us,
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output wire [7:0] sshr_su,
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output wire signed [7:0] sshr_ss,
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output wire [7:0] shiftx_uu,
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output wire signed [7:0] shiftx_us,
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output wire [7:0] shiftx_su,
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output wire signed [7:0] shiftx_ss
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);
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assign shl_uu = in_u << 20;
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assign shl_us = in_u << 20;
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assign shl_su = in_s << 20;
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assign shl_ss = in_s << 20;
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assign shr_uu = in_u >> 20;
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assign shr_us = in_u >> 20;
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assign shr_su = in_s >> 20;
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assign shr_ss = in_s >> 20;
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assign sshl_uu = in_u <<< 20;
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assign sshl_us = in_u <<< 20;
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assign sshl_su = in_s <<< 20;
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assign sshl_ss = in_s <<< 20;
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assign sshr_uu = in_u >>> 20;
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assign sshr_us = in_u >>> 20;
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assign sshr_su = in_s >>> 20;
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assign sshr_ss = in_s >>> 20;
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wire [7:0] shamt = 20;
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assign shiftx_uu = in_u[shamt +: 8];
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assign shiftx_us = in_u[shamt +: 8];
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assign shiftx_su = in_s[shamt +: 8];
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assign shiftx_ss = in_s[shamt +: 8];
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endmodule
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EOT
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select -assert-count 4 t:$shl
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select -assert-count 4 t:$shr
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select -assert-count 4 t:$sshl
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select -assert-count 4 t:$sshr
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select -assert-count 4 t:$shiftx
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equiv_opt opt_expr
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design -load postopt
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select -assert-none t:$shl
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select -assert-none t:$shr
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select -assert-none t:$sshl
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select -assert-none t:$sshr
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select -assert-none t:$shiftx
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design -reset
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read_verilog <<EOT
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module top (
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input wire [3:0] in,
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output wire [7:0] shl,
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output wire [7:0] shr,
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output wire [7:0] sshl,
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output wire [7:0] sshr,
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output wire [7:0] shiftx,
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output wire [7:0] shl_s,
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output wire [7:0] shr_s,
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output wire [7:0] sshl_s,
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output wire [7:0] sshr_s,
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output wire [7:0] shiftx_s,
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);
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assign shl = in << 36'hfffffffff;
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assign shr = in >> 36'hfffffffff;
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assign sshl = in <<< 36'hfffffffff;
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assign sshr = in >>> 36'hfffffffff;
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assign shiftx = in[36'hfffffffff +: 8];
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wire signed [35:0] shamt = 36'hfffffffff;
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assign shl_s = in << shamt;
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assign shr_s = in >> shamt;
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assign sshl_s = in <<< shamt;
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assign sshr_s = in >>> shamt;
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assign shiftx_s = in[shamt +: 8];
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endmodule
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EOT
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select -assert-count 2 t:$shl
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select -assert-count 2 t:$shr
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select -assert-count 2 t:$sshl
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select -assert-count 2 t:$sshr
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select -assert-count 1 t:$shiftx
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equiv_opt opt_expr
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design -load postopt
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select -assert-none t:$shl
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select -assert-none t:$shr
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select -assert-none t:$sshl
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select -assert-none t:$sshr
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select -assert-none t:$shiftx
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design -reset
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read_verilog <<EOT
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module top (
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input wire [3:0] in,
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output wire [7:0] shl,
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output wire [7:0] shr,
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output wire [7:0] sshl,
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output wire [7:0] sshr,
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output wire [7:0] shiftx,
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output wire [7:0] shl_s,
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output wire [7:0] shr_s,
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output wire [7:0] sshl_s,
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output wire [7:0] sshr_s,
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output wire [7:0] shiftx_s,
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);
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assign shl = in << 32'hffffffff;
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assign shr = in >> 32'hffffffff;
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assign sshl = in <<< 32'hffffffff;
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assign sshr = in >>> 32'hffffffff;
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assign shiftx = in[32'hffffffff +: 8];
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wire signed [31:0] shamt = 32'hffffffff;
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assign shl_s = in << shamt;
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assign shr_s = in >> shamt;
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assign sshl_s = in <<< shamt;
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assign sshr_s = in >>> shamt;
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assign shiftx_s = in[shamt +: 8];
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endmodule
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EOT
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select -assert-count 2 t:$shl
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select -assert-count 2 t:$shr
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select -assert-count 2 t:$sshl
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select -assert-count 2 t:$sshr
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select -assert-count 1 t:$shiftx
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equiv_opt opt_expr
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design -load postopt
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select -assert-none t:$shl
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select -assert-none t:$shr
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select -assert-none t:$sshl
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select -assert-none t:$sshr
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select -assert-none t:$shiftx
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