mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
168 lines
3.2 KiB
Text
168 lines
3.2 KiB
Text
read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b0} + 1'b1;
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b1} + 1'b1;
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endmodule
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EOT
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alumacc
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select -assert-count 1 t:$alu
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select -assert-none t:$alu t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b1} - 1'b1;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [3:0] y);
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assign y = {a,3'b101} - 1'b1;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [3:0] y);
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assign y = {a,3'b101} - 1'b1;
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$not
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select -assert-none t:$not %% t:* %D
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design -reset
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read_verilog <<EOT
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module test(input [1:0] a, output [3:0] y);
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assign y = -{a[1], 2'b10, a[0]};
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt -fine
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design -load postopt
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select -assert-count 1 t:$alu
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select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
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select -assert-count 1 t:$not
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select -assert-none t:$alu t:$not t:* %D %D
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design -reset
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read_verilog <<EOT
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module test(input [3:0] a, input [2:0] b, output [5:0] y);
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assign y = {a[3:2], 1'b1, a[1:0]} + {b[2], 2'b11, b[1:0]};
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt -fine
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design -load postopt
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dump
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select -assert-count 2 t:$alu
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select -assert-count 1 t:$alu r:Y_WIDTH=2 %i
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select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
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select -assert-none t:$alu t:* %D
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design -reset
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read_verilog <<EOT
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module test(input [3:0] a, input [3:0] b, output [5:0] y);
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assign y = {a[3:2], 1'b0, a[1:0]} + {b[3:2], 1'b0, b[1:0]};
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt -fine
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design -load postopt
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select -assert-count 2 t:$alu
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select -assert-count 2 t:$alu r:Y_WIDTH=3 %i
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select -assert-none t:$alu t:* %D
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design -reset
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read_verilog -icells <<EOT
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module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
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$alu #(
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.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
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.A_SIGNED(0), .B_SIGNED(0),
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) alu (
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.A(a), .B(4'h0),
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.BI(1'b0), .CI(1'b0),
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.Y(y), .X(x), .CO(co),
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);
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endmodule
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EOT
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equiv_opt -assert opt
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design -load postopt
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select -assert-none t:$alu
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design -reset
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read_verilog -icells <<EOT
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module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
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$alu #(
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.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
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.A_SIGNED(0), .B_SIGNED(0),
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) alu (
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.A(a), .B(4'h0),
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.BI(1'b1), .CI(1'b1),
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.Y(y), .X(x), .CO(co),
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);
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endmodule
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EOT
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equiv_opt -assert opt
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design -load postopt
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select -assert-none t:$alu
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design -reset
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read_verilog -icells <<EOT
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module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
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$alu #(
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.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
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.A_SIGNED(0), .B_SIGNED(0),
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) alu (
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.A(4'h0), .B(a),
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.BI(1'b0), .CI(1'b0),
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.Y(y), .X(x), .CO(co),
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);
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endmodule
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EOT
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equiv_opt -assert opt
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design -load postopt
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select -assert-none t:$alu
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