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26 lines
682 B
Verilog
26 lines
682 B
Verilog
// expect-wr-ports 1
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// expect-rd-ports 1
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module generic_sram_byte_en #(
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parameter DATA_WIDTH = 32,
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parameter ADDRESS_WIDTH = 4
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) (
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input i_clk,
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input [DATA_WIDTH-1:0] i_write_data,
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input i_write_enable,
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input [ADDRESS_WIDTH-1:0] i_address,
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input [DATA_WIDTH/8-1:0] i_byte_enable,
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output reg [DATA_WIDTH-1:0] o_read_data
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);
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reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1];
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integer i;
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always @(posedge i_clk) begin
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for (i=0;i<DATA_WIDTH/8;i=i+1)
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if (i_write_enable && i_byte_enable[i])
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mem[i_address][i*8 +: 8] <= i_write_data[i*8 +: 8];
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o_read_data <= mem[i_address];
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end
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endmodule
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