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.gitignore
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abc9_dff.ys
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Fix tests for check in equiv_opt
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2022-10-07 16:04:51 +02:00 |
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add_sub.ys
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adffs.ys
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asym_ram_sdp.ys
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Asymmetric port ram tests with Xilinx
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2023-02-21 05:23:14 +13:00 |
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asym_ram_sdp_read_wider.v
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Asymmetric port ram tests with Xilinx
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2023-02-21 05:23:14 +13:00 |
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asym_ram_sdp_write_wider.v
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Asymmetric port ram tests with Xilinx
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2023-02-21 05:23:14 +13:00 |
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attributes_test.ys
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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blockram.ys
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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bug1460.ys
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bug1462.ys
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bug1480.ys
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bug1598.ys
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bug1605.ys
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bug3670.v
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ABC9: Cell Port Bug Patch (#3670)
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2023-04-22 16:24:36 -07:00 |
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bug3670.ys
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ABC9: Cell Port Bug Patch (#3670)
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2023-04-22 16:24:36 -07:00 |
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counter.ys
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dffs.ys
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dsp_abc9.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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dsp_cascade.ys
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dsp_fastfir.ys
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dsp_simd.ys
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fsm.ys
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FfData: some refactoring.
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2021-10-07 04:24:06 +02:00 |
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latches.ys
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opt_expr: Remove -clkinv option, make it the default.
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2020-07-31 00:08:15 +02:00 |
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logic.ys
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lutram.ys
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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macc.sh
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macc.v
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macc.ys
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macc_tb.v
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mul.ys
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mul_unsigned.v
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mul_unsigned.ys
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mux.ys
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xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
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2021-01-27 00:32:00 +01:00 |
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mux_lut4.ys
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Update tests
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2023-06-09 14:41:45 +02:00 |
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nosrl.ys
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xilinx: Fix srl regression.
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2020-07-12 23:41:27 +02:00 |
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opt_lut_ins.ys
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Remove references to ilang
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2024-11-05 12:36:31 +13:00 |
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pmgen_xilinx_srl.ys
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satgen: Add support for dffe, sdff, sdffe, sdffce cells.
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2020-07-24 03:19:21 +02:00 |
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priority_memory.v
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Tests for ram_style = "huge"
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2023-02-21 05:23:15 +13:00 |
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priority_memory.ys
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Tests for ram_style = "huge"
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2023-02-21 05:23:15 +13:00 |
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run-test.sh
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tests: Centralize test collection and Makefile generation
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2020-09-21 15:07:02 +02:00 |
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shifter.ys
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tribuf.sh
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Fix the tests we just broke
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2021-12-10 00:22:37 +01:00 |
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tribuf.ys
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xilinx_dffopt.ys
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Fix tests for check in equiv_opt
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2022-10-07 16:04:51 +02:00 |
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xilinx_dffopt_blacklist.txt
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xilinx_dsp.ys
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xilinx_srl.v
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xilinx_srl.ys
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