mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 01:54:10 +00:00
38a0c30d65
This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
392 lines
11 KiB
C++
392 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2018 David Shah <dave@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthEcp5Pass : public ScriptPass
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{
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SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_ecp5 [options]\n");
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log("\n");
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log("This command runs synthesis for ECP5 FPGAs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -blif <file>\n");
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log(" write the design to the specified BLIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified EDIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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log(" -noccu2\n");
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log(" do not use CCU2 cells in output netlist\n");
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log("\n");
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log(" -nodffe\n");
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log(" do not use flipflops with CE in output netlist\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use block RAM cells in output netlist\n");
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log("\n");
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log(" -nolutram\n");
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log(" do not use LUT RAM cells in output netlist\n");
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log("\n");
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log(" -nowidelut\n");
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log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
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log("\n");
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log(" -asyncprld\n");
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log(" use async PRLD mode to implement DLATCH and DFFSR (EXPERIMENTAL)\n");
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log("\n");
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log(" -abc2\n");
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log(" run two passes of 'abc' for slightly improved logic density\n");
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log("\n");
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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log("\n");
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log(" -vpr\n");
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log(" generate an output netlist (and BLIF file) suitable for VPR\n");
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log(" (this feature is experimental and incomplete)\n");
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log("\n");
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log(" -nodsp\n");
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log(" do not map multipliers to MULT18X18D\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, blif_file, edif_file, json_file;
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bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, retime, abc2, abc9, nodsp, vpr;
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void clear_flags() YS_OVERRIDE
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{
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top_opt = "-auto-top";
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blif_file = "";
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edif_file = "";
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json_file = "";
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noccu2 = false;
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nodffe = false;
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nobram = false;
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nolutram = false;
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nowidelut = false;
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asyncprld = false;
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flatten = true;
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retime = false;
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abc2 = false;
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vpr = false;
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abc9 = false;
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nodsp = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-blif" && argidx+1 < args.size()) {
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blif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-edif" && argidx+1 < args.size()) {
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edif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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if (args[argidx] == "-noccu2") {
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noccu2 = true;
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continue;
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}
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if (args[argidx] == "-nodffe") {
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nodffe = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-asyncprld") {
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asyncprld = true;
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continue;
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}
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if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
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nolutram = true;
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continue;
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}
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if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
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nowidelut = true;
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continue;
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}
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if (args[argidx] == "-abc2") {
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abc2 = true;
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continue;
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}
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if (args[argidx] == "-vpr") {
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vpr = true;
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc9 = true;
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continue;
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}
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if (args[argidx] == "-nodsp") {
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nodsp = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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if (abc9 && retime)
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log_cmd_error("-retime option not currently compatible with -abc9!\n");
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log_header(design, "Executing SYNTH_ECP5 pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() YS_OVERRIDE
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (check_label("coarse"))
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{
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run("proc");
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if (flatten || help_mode)
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run("flatten");
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run("tribuf -logic");
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run("deminout");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt");
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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run("share");
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
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run("opt_expr");
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run("opt_clean");
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if (!nodsp) {
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run("techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
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run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
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}
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run("alumacc");
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run("opt");
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run("fsm");
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run("opt -fast");
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run("memory -nomap");
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run("opt_clean");
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}
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if (!nobram && check_label("map_bram", "(skip if -nobram)"))
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{
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run("memory_bram -rules +/ecp5/brams.txt");
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run("techmap -map +/ecp5/brams_map.v");
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}
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if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
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{
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run("memory_bram -rules +/ecp5/lutrams.txt");
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run("techmap -map +/ecp5/lutrams_map.v");
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}
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if (check_label("map_ffram"))
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{
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run("opt -fast -mux_undef -undriven -fine");
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run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block "
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"-attr syn_ramstyle=auto -attr syn_ramstyle=registers "
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"-attr syn_romstyle=auto -attr syn_romstyle=logic");
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run("opt -undriven -fine");
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}
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if (check_label("map_gates"))
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{
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if (noccu2)
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run("techmap");
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else
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run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
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run("opt -fast");
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if (retime || help_mode)
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run("abc -dff -D 1", "(only if -retime)");
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}
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if (check_label("map_ffs"))
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{
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run("dff2dffs");
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run("opt_clean");
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if (!nodffe)
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run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
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run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : "")));
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run("opt_expr -undriven -mux_undef");
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run("simplemap");
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run("ecp5_ffinit");
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run("ecp5_gsr");
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run("attrmvcp -copy -attr syn_useioff");
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run("opt_clean");
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}
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if (check_label("map_luts"))
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{
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if (abc2 || help_mode) {
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run("abc", " (only if -abc2)");
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}
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std::string techmap_args = asyncprld ? "" : "-map +/ecp5/latches_map.v";
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if (abc9)
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techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
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if (!asyncprld || abc9)
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run("techmap " + techmap_args);
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if (abc9) {
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run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
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if (nowidelut)
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run("abc9 -maxlut 4 -W 200");
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else
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run("abc9 -W 200");
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run("techmap -map +/ecp5/abc9_unmap.v");
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} else {
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if (nowidelut)
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run("abc -lut 4 -dress");
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else
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run("abc -lut 4:7 -dress");
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}
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run("clean");
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}
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if (check_label("map_cells"))
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{
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if (vpr)
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run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
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else
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run("techmap -map +/ecp5/cells_map.v", "(with -D NO_LUT in vpr mode)");
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run("opt_lut_ins -tech ecp5");
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run("clean");
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}
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if (check_label("check"))
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{
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run("autoname");
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
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}
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if (check_label("blif"))
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{
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if (!blif_file.empty() || help_mode) {
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if (vpr || help_mode) {
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run(stringf("opt_clean -purge"),
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" (vpr mode)");
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run(stringf("write_blif -attr -cname -conn -param %s",
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help_mode ? "<file-name>" : blif_file.c_str()),
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" (vpr mode)");
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}
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if (!vpr)
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run(stringf("write_blif -gates -attr -param %s",
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help_mode ? "<file-name>" : blif_file.c_str()),
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" (non-vpr mode)");
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}
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}
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if (check_label("edif"))
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{
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if (!edif_file.empty() || help_mode)
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run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
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}
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if (check_label("json"))
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{
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if (!json_file.empty() || help_mode)
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run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
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}
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}
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} SynthEcp5Pass;
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PRIVATE_NAMESPACE_END
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