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331ac5285f
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions. |
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| .. | ||
| .gitignore | ||
| abc9_dff.ys | ||
| add_sub.ys | ||
| adffs.ys | ||
| asym_ram_sdp.ys | ||
| asym_ram_sdp_read_wider.v | ||
| asym_ram_sdp_write_wider.v | ||
| attributes_test.ys | ||
| blockram.ys | ||
| bug1460.ys | ||
| bug1462.ys | ||
| bug1480.ys | ||
| bug1598.ys | ||
| bug1605.ys | ||
| bug3670.v | ||
| bug3670.ys | ||
| counter.ys | ||
| dffs.ys | ||
| dsp_abc9.ys | ||
| dsp_cascade.ys | ||
| dsp_fastfir.ys | ||
| dsp_simd.ys | ||
| fsm.ys | ||
| latches.ys | ||
| logic.ys | ||
| lutram.ys | ||
| macc.sh | ||
| macc.v | ||
| macc.ys | ||
| macc_tb.v | ||
| mul.ys | ||
| mul_unsigned.v | ||
| mul_unsigned.ys | ||
| mux.ys | ||
| mux_lut4.ys | ||
| nosrl.ys | ||
| opt_lut_ins.ys | ||
| pmgen_xilinx_srl.ys | ||
| priority_memory.v | ||
| priority_memory.ys | ||
| run-test.sh | ||
| shifter.ys | ||
| tribuf.sh | ||
| tribuf.ys | ||
| xilinx_dffopt.ys | ||
| xilinx_dffopt_blacklist.txt | ||
| xilinx_dsp.ys | ||
| xilinx_srl.v | ||
| xilinx_srl.ys | ||