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64 lines
1.2 KiB
Verilog
64 lines
1.2 KiB
Verilog
module test (
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input EN, CLK,
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input [3:0] D,
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output reg [3:0] Q
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);
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always @(posedge CLK)
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if (EN) Q <= D;
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specify
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if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
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$setup(D, posedge CLK &&& EN, 5);
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$hold(posedge CLK, D &&& EN, 6);
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endspecify
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endmodule
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module test2 (
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input A, B,
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output Q
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);
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xor (Q, A, B);
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specify
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//specparam T_rise = 1;
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//specparam T_fall = 2;
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`define T_rise 1
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`define T_fall 2
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(A => Q) = (`T_rise,`T_fall);
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//(B => Q) = (`T_rise+`T_fall)/2.0;
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(B => Q) = 1.5;
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endspecify
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endmodule
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module issue01144(input clk, d, output q);
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specify
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(posedge clk => (q +: d)) = (3,1);
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(posedge clk *> (q +: d)) = (3,1);
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endspecify
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endmodule
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module test3(input clk, input [1:0] d, output [1:0] q);
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specify
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(posedge clk => (q +: d)) = (3,1);
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(posedge clk *> (q +: d)) = (3,1);
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endspecify
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endmodule
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module test4(input clk, d, output q);
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specify
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$setup(d, posedge clk, 1:2:3);
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$setuphold(d, posedge clk, 1:2:3, 4:5:6);
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endspecify
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endmodule
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module test5(input clk, d, e, output q);
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specify
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$setup(d, posedge clk &&& e, 1:2:3);
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endspecify
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endmodule
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module test6(input clk, d, e, output q);
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specify
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(d[0] *> q[0]) = (3,1);
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(posedge clk[0] => (q[0] +: d[0])) = (3,1);
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endspecify
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endmodule
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