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53 lines
1.6 KiB
Verilog
53 lines
1.6 KiB
Verilog
//-----------------------------------------------------
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// Design Name : parallel_crc_ccitt
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// File Name : parallel_crc.v
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// Function : CCITT Parallel CRC
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module parallel_crc_ccitt (
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clk ,
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reset ,
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enable ,
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init ,
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data_in ,
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crc_out
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);
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//-----------Input Ports---------------
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input clk ;
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input reset ;
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input enable ;
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input init ;
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input [7:0] data_in ;
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//-----------Output Ports---------------
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output [15:0] crc_out;
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//------------Internal Variables--------
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reg [15:0] crc_reg;
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wire [15:0] next_crc;
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//-------------Code Start-----------------
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assign crc_out = crc_reg;
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// CRC Control logic
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always @ (posedge clk)
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if (reset) begin
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crc_reg <= 16'hFFFF;
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end else if (enable) begin
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if (init) begin
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crc_reg <= 16'hFFFF;
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end else begin
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crc_reg <= next_crc;
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end
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end
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// Parallel CRC calculation
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assign next_crc[0] = data_in[7] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[11];
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assign next_crc[1] = data_in[1] ^ crc_reg[5];
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assign next_crc[2] = data_in[2] ^ crc_reg[6];
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assign next_crc[3] = data_in[3] ^ crc_reg[7];
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assign next_crc[4] = data_in[4] ^ crc_reg[8];
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assign next_crc[5] = data_in[7] ^ data_in[5] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[9] ^ crc_reg[11];
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assign next_crc[6] = data_in[6] ^ data_in[1] ^ crc_reg[5] ^ crc_reg[10];
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assign next_crc[7] = data_in[7] ^ data_in[2] ^ crc_reg[6] ^ crc_reg[11];
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assign next_crc[8] = data_in[3] ^ crc_reg[0] ^ crc_reg[7];
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assign next_crc[9] = data_in[4] ^ crc_reg[1] ^ crc_reg[8];
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assign next_crc[10] = data_in[5] ^ crc_reg[2] ^ crc_reg[9];
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assign next_crc[11] = data_in[6] ^ crc_reg[3] ^ crc_reg[10];
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endmodule
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