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35 lines
1.4 KiB
Text
35 lines
1.4 KiB
Text
read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_MUL9X9
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select -assert-none t:MISTRAL_MUL9X9 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_MUL18X18
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select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_MUL27X27
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select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
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