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			96 lines
		
	
	
	
		
			2.6 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			96 lines
		
	
	
	
		
			2.6 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
(* techmap_celltype = "$_DFFE_[PN][PN][01][PN]_" *)
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module  \$_DFFE_xxxx_ (input D, C, R, E, output Q);
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  parameter _TECHMAP_CELLTYPE_ = "";
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  EFX_FF #(
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    .CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"),
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    .CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"),
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    .SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"),
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    .D_POLARITY(1'b1),
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    .SR_SYNC(1'b0),
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    .SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"),
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    .SR_SYNC_PRIORITY(1'b1)
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  ) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));
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  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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endmodule
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(* techmap_celltype = "$_SDFFE_[PN][PN][01][PN]_" *)
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module  \$_SDFFE_xxxx_ (input D, C, R, E, output Q);
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  parameter _TECHMAP_CELLTYPE_ = "";
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  EFX_FF #(
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    .CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"),
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    .CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"),
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    .SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"),
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    .D_POLARITY(1'b1),
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    .SR_SYNC(1'b1),
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    .SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"),
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    .SR_SYNC_PRIORITY(1'b1)
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  ) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));
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  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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endmodule
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(* techmap_celltype = "$_SDFFCE_[PN][PN][01][PN]_" *)
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module  \$_SDFFCE_xxxx_ (input D, C, R, E, output Q);
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  parameter _TECHMAP_CELLTYPE_ = "";
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  EFX_FF #(
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    .CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"),
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    .CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"),
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    .SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"),
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    .D_POLARITY(1'b1),
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    .SR_SYNC(1'b1),
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    .SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"),
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    .SR_SYNC_PRIORITY(1'b0)
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  ) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));
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  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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endmodule
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module \$_DLATCH_N_ (E, D, Q);
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  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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  input E, D;
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  output Q = !E ? D : Q;
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endmodule
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module \$_DLATCH_P_ (E, D, Q);
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  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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  input E, D;
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  output Q = E ? D : Q;
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endmodule
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`ifndef NO_LUT
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module \$lut (A, Y);
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  parameter WIDTH = 0;
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  parameter LUT = 0;
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  (* force_downto *)
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  input [WIDTH-1:0] A;
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  output Y;
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  generate
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    if (WIDTH == 1) begin
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      EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
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    end else
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    if (WIDTH == 2) begin
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      EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
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    end else
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    if (WIDTH == 3) begin
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      EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
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    end else
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    if (WIDTH == 4) begin
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      EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
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    end else begin
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      wire _TECHMAP_FAIL_ = 1;
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    end
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  endgenerate
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endmodule
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`endif
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