Andrew Pullin 6ac8c8cb05 ast: Add support for array-to-array assignment ... This commit adds support for SystemVerilog array-to-array assignment operations that were previously unsupported: 1. Direct array assignment: `b = a;` 2. Array ternary expressions: `out = sel ? a : b;` Both single-dimensional and multi-dimensional unpacked arrays are supported. The implementation expands these array operations during AST simplification into element-wise assignments. Example of now-supported syntax: ```systemverilog wire [7:0] state_regs[8]; wire [7:0] r[8]; wire [7:0] sel[8]; assign sel = condition ? state_regs : r; ``` Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>		2026-03-04 21:34:40 -08:00
..
array_assign.sv	ast: Add support for array-to-array assignment	2026-03-04 21:34:40 -08:00
enum_simple.sv
enum_simple.ys
logic_rom.sv
logic_rom.ys
multirange_array.sv
multirange_subarray_access.ys
run-test.sh
static_cast_negative.ys
static_cast_nonconst.ys
static_cast_simple.sv
static_cast_verilog.ys
static_cast_zero.ys
struct_array.sv
struct_dynamic_range.sv
struct_dynamic_range.ys
struct_simple.sv
struct_sizebits.sv
typedef_initial_and_assign.sv
typedef_initial_and_assign.ys	tests: remove -seq 1 from sat with -tempinduct where possible	2025-09-08 18:04:32 +02:00
typedef_memory.sv
typedef_memory.ys
typedef_memory_2.sv
typedef_memory_2.ys
typedef_package.sv
typedef_param.sv
typedef_scopes.sv
typedef_simple.sv
typedef_struct.sv
typedef_struct_global.ys
typedef_struct_port.sv
typedef_struct_port.ys	tests: remove -seq 1 from sat with -tempinduct where possible	2025-09-08 18:04:32 +02:00
union_simple.sv