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yosys/frontends/verilog
2026-02-27 20:42:52 +03:00
..
.gitignore
const2ast.cc
Makefile.inc
preproc.cc reduce OS ifdefs, refactor getting dirs and filenames from paths to files 2025-10-14 15:46:17 +02:00
preproc.h
verilog_error.cc
verilog_error.h
verilog_frontend.cc read_verilog: remove log I left behind by accident 2026-01-13 18:47:23 +01:00
verilog_frontend.h
verilog_lexer.h
verilog_lexer.l verilog: Bufnorm cell backend and frontend support 2025-09-17 14:01:09 +02:00
verilog_location.h
verilog_parser.y support automatic lifetime qualifier on procedural variables 2026-02-27 20:42:52 +03:00