Eddie Hung eb4e767053 Do not offset FD* box timings due to -46ps Tsu		2019-12-30 14:35:10 -08:00
..
tests	xilinx: Test our DSP48A/DSP48A1 simulation models.	2019-12-23 20:36:43 +01:00
.gitignore
abc9_map.v	Tidy up abc9_map.v	2019-12-30 14:19:29 -08:00
abc9_model.v	Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t	2019-12-19 11:23:41 -08:00
abc9_unmap.v	Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t	2019-12-19 11:23:41 -08:00
abc9_xc7.box	Do not offset FD* box timings due to -46ps Tsu	2019-12-30 14:35:10 -08:00
abc9_xc7.lut
abc9_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v
cells_sim.v	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-12-30 14:31:42 -08:00
cells_xtra.py
cells_xtra.v
lut_map.v
lutrams.txt
lutrams_map.v
Makefile.inc
mux_map.v
synth_xilinx.cc	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-12-30 14:31:42 -08:00
xc3s_mult_map.v
xc3sda_dsp_map.v	xilinx_dsp: Initial DSP48A/DSP48A1 support.	2019-12-22 20:51:14 +01:00
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_brams.txt
xc6s_brams_map.v
xc6s_dsp_map.v	xilinx_dsp: Initial DSP48A/DSP48A1 support.	2019-12-22 20:51:14 +01:00
xc6s_ff_map.v
xc7_brams_map.v
xc7_dsp_map.v
xc7_ff_map.v
xc7_xcu_brams.txt
xcu_brams_map.v
xcu_dsp_map.v
xcup_urams.txt
xcup_urams_map.v
xilinx_dffopt.cc