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3787ea19cd
Change tests/memfile to a mktest, moving the prior run-test.sh contents into a new read_dir.sh. Add dump.ys (and friends) for testing dump_meminit.
19 lines
No EOL
282 B
Verilog
19 lines
No EOL
282 B
Verilog
module gate (
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input clk, wen,
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input [2:0] addr,
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input [3:0] wdata,
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output [3:0] rdata
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);
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reg [3:0] m [7:0];
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initial
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$readmemh("gold.m.mem", m);
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always @(posedge clk) begin
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if (wen)
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m[addr] <= wdata;
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else
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rdata <= m[addr];
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end
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endmodule |