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yosys/techlibs/common
Marcelina Kościelnicka cde73428b0 Fix syntax error in adff2dff.v
Fixes #2600.
2021-02-24 01:07:34 +01:00
..
.gitignore
abc9_map.v techmap: Add support for [] wildcards in techmap_celltype. 2020-08-02 22:46:48 +02:00
abc9_model.v
abc9_unmap.v
adff2dff.v Fix syntax error in adff2dff.v 2021-02-24 01:07:34 +01:00
cellhelp.py
cells.lib
cmp2lcu.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
cmp2lut.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
dff2ff.v
gate2lut.v
gen_fine_ffs.py simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
Makefile.inc
mul2dsp.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
pmux2mux.v
prep.cc
simcells.v simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
simlib.v Fix some trivial typos. 2021-01-03 23:52:59 -08:00
synth.cc Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
techmap.v techmap/shift_shiftx: Remove the "shiftx2mux" special path. 2020-08-20 12:44:09 +02:00