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10 lines
271 B
Verilog
10 lines
271 B
Verilog
module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
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assign o = i[s*W+:W];
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endmodule
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module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
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wire [3:0] t;
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assign t = i * 3;
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assign o = t / 3;
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endmodule
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