mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity
yosys/tests/arch/intel_alm
History
Dan Ravensloft 1a07b330f8 intel_alm: Add multiply signedness to cells 
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
2020-08-26 22:50:16 +02:00
..
.gitignore Add missing .gitignore file 2020-06-04 22:25:47 +02:00
add_sub.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
adffs.ys Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
blockram.ys intel_alm: direct M10K instantiation 2020-07-27 15:39:06 +02:00
counter.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
dffs.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
fsm.ys Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
logic.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
lutram.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
mul.ys intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
mux.ys techmap/shift_shiftx: Remove the "shiftx2mux" special path. 2020-08-20 12:44:09 +02:00
quartus_ice.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
run-test.sh synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
shifter.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
tribuf.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00