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yosys/passes
History
Emil J. Tywoniak 3582b5df71 timeest: leave signorm mode 
Every cell needs an AIG model or the pass errors out, and the signorm
marker cells are bookkeeping with no timing behaviour and no model:
`Unsupported cell '$input_port' in module 'top2'` (various/timeest).
Joining the ~20 passes that already opt out is cheaper than teaching the
estimator which cell types are not logic.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
2026-07-21 16:52:45 +02:00
..
cmds timeest: leave signorm mode 2026-07-21 16:52:45 +02:00
equiv twine: fix replayability, reduce TwineSearch usage 2026-07-20 13:57:10 +02:00
fsm passes: leave signorm mode where the index cannot be maintained 2026-07-21 14:05:07 +02:00
hierarchy passes: leave signorm mode where the index cannot be maintained 2026-07-21 14:05:07 +02:00
memory memory_libmap: provide blackboxes for the RAM cells it instantiates 2026-07-21 14:05:07 +02:00
opt opt_clean: trace $connect edges from the liveness roots too 2026-07-21 16:52:18 +02:00
pmgen WIP migration to twine 2026-07-20 13:57:10 +02:00
proc proc_mux: WIP 2026-07-20 15:01:30 +02:00
sat twine: fix replayability, reduce TwineSearch usage 2026-07-20 13:57:10 +02:00
techmap techmap: decode derived_name in the map pool, not the target design 2026-07-20 15:01:30 +02:00
tests twines phase-3 build fix: post-fork main files broken by twine migration 2026-07-20 15:01:30 +02:00
CMakeLists.txt