mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
234 lines
8 KiB
C++
234 lines
8 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2017 Robert Ou <rqou@robertou.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Coolrunner2SopPass : public Pass {
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Coolrunner2SopPass() : Pass("coolrunner2_sop", "break $sop cells into ANDTERM/ORTERM cells") { }
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void help() override
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{
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log("\n");
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log(" coolrunner2_sop [options] [selection]\n");
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log("\n");
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log("Break $sop cells into ANDTERM/ORTERM cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing COOLRUNNER2_SOP pass (break $sop cells into ANDTERM/ORTERM cells).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules())
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{
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pool<Cell*> cells_to_remove;
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SigMap sigmap(module);
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// Find all the $_NOT_ cells
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dict<SigBit, tuple<SigBit, Cell*>> not_cells;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == ID($_NOT_))
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{
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auto not_input = sigmap(cell->getPort(ID::A)[0]);
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auto not_output = sigmap(cell->getPort(ID::Y)[0]);
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not_cells[not_input] = tuple<SigBit, Cell*>(not_output, cell);
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}
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}
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// Find wires that need to become special product terms
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dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_no_inv;
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dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_inv;
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(FTCP), ID(FTCP_N), ID(FTDCP),
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ID(FDCPE), ID(FDCPE_N), ID(FDDCPE), ID(LDCP), ID(LDCP_N)))
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{
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if (cell->hasPort(ID(PRE)))
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special_pterms_no_inv[sigmap(cell->getPort(ID(PRE))[0])].insert(
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make_tuple(cell, ID(PRE)));
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if (cell->hasPort(ID::CLR))
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special_pterms_no_inv[sigmap(cell->getPort(ID::CLR)[0])].insert(
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make_tuple(cell, ID::CLR));
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if (cell->hasPort(ID(CE)))
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special_pterms_no_inv[sigmap(cell->getPort(ID(CE))[0])].insert(
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make_tuple(cell, ID(CE)));
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if (cell->hasPort(ID::C))
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special_pterms_inv[sigmap(cell->getPort(ID::C)[0])].insert(
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make_tuple(cell, ID::C));
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if (cell->hasPort(ID::G))
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special_pterms_inv[sigmap(cell->getPort(ID::G)[0])].insert(
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make_tuple(cell, ID::G));
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}
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}
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// Process $sop cells
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for (auto cell : module->selected_cells())
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{
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if (cell->type == ID($sop))
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{
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// Read the inputs/outputs/parameters of the $sop cell
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auto sop_inputs = sigmap(cell->getPort(ID::A));
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auto sop_output = sigmap(cell->getPort(ID::Y))[0];
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auto sop_depth = cell->getParam(ID::DEPTH).as_int();
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auto sop_width = cell->getParam(ID::WIDTH).as_int();
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auto sop_table = cell->getParam(ID::TABLE);
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auto sop_output_wire_name = sop_output.wire->name.c_str();
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// Check for a $_NOT_ at the output
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bool has_invert = false;
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if (not_cells.count(sop_output))
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{
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auto not_cell = not_cells.at(sop_output);
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has_invert = true;
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sop_output = std::get<0>(not_cell);
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// remove the $_NOT_ cell because it gets folded into the xor
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cells_to_remove.insert(std::get<1>(not_cell));
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}
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// Check for special P-term usage
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bool is_special_pterm =
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special_pterms_no_inv.count(sop_output) || special_pterms_inv.count(sop_output);
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// Construct AND cells
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pool<SigBit> intermed_wires;
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for (int i = 0; i < sop_depth; i++) {
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// Wire for the output
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auto and_out = module->addWire(
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module->uniquify(stringf("$xc2sop$%s_AND%d_OUT", sop_output_wire_name, i)));
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intermed_wires.insert(and_out);
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// Signals for the inputs
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pool<SigBit> and_in_true;
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pool<SigBit> and_in_comp;
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for (int j = 0; j < sop_width; j++)
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{
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if (sop_table[2 * (i * sop_width + j) + 0])
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{
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and_in_comp.insert(sop_inputs[j]);
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}
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if (sop_table[2 * (i * sop_width + j) + 1])
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{
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and_in_true.insert(sop_inputs[j]);
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}
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}
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// Construct the cell
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auto and_cell = module->addCell(
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module->uniquify(stringf("$xc2sop$%s_AND%d", sop_output_wire_name, i)),
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ID(ANDTERM));
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and_cell->setParam(ID(TRUE_INP), GetSize(and_in_true));
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and_cell->setParam(ID(COMP_INP), GetSize(and_in_comp));
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and_cell->setPort(ID(OUT), and_out);
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and_cell->setPort(ID(IN), and_in_true);
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and_cell->setPort(ID(IN_B), and_in_comp);
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}
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if (sop_depth == 1)
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{
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// If there is only one term, don't construct an OR cell. Directly construct the XOR gate
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auto xor_cell = module->addCell(
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module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
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ID(MACROCELL_XOR));
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xor_cell->setParam(ID(INVERT_OUT), has_invert);
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xor_cell->setPort(ID(IN_PTC), *intermed_wires.begin());
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xor_cell->setPort(ID(OUT), sop_output);
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// Special P-term handling
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if (is_special_pterm)
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{
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// Can always connect the P-term directly if it's going
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// into something invert-capable
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for (const auto &x : special_pterms_inv[sop_output])
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{
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std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
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// If this signal is indeed inverted, flip the cell polarity
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if (has_invert)
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{
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auto cell = std::get<0>(x);
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if (cell->type == ID(FDCP)) cell->type = ID(FDCP_N);
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else if (cell->type == ID(FDCP_N)) cell->type = ID(FDCP);
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else if (cell->type == ID(FTCP)) cell->type = ID(FTCP_N);
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else if (cell->type == ID(FTCP_N)) cell->type = ID(FTCP);
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else if (cell->type == ID(FDCPE)) cell->type = ID(FDCPE_N);
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else if (cell->type == ID(FDCPE_N)) cell->type = ID(FDCPE);
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else if (cell->type == ID(LDCP)) cell->type = ID(LDCP_N);
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else if (cell->type == ID(LDCP_N)) cell->type = ID(LDCP);
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else log_assert(!"Internal error! Bad cell type!");
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}
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}
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// If it's going into something that's not invert-capable,
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// connect it directly only if this signal isn't inverted
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if (!has_invert)
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{
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for (auto x : special_pterms_no_inv[sop_output])
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std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
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}
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// Otherwise, a feedthrough P-term has to be created. Leave that to happen
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// in the coolrunner2_fixup pass.
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}
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}
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else
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{
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// Wire from OR to XOR
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auto or_to_xor_wire = module->addWire(
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module->uniquify(stringf("$xc2sop$%s_OR_OUT", sop_output_wire_name)));
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// Construct the OR cell
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auto or_cell = module->addCell(
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module->uniquify(stringf("$xc2sop$%s_OR", sop_output_wire_name)),
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ID(ORTERM));
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or_cell->setParam(ID::WIDTH, sop_depth);
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or_cell->setPort(ID(IN), intermed_wires);
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or_cell->setPort(ID(OUT), or_to_xor_wire);
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// Construct the XOR cell
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auto xor_cell = module->addCell(
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module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
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ID(MACROCELL_XOR));
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xor_cell->setParam(ID(INVERT_OUT), has_invert);
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xor_cell->setPort(ID(IN_ORTERM), or_to_xor_wire);
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xor_cell->setPort(ID(OUT), sop_output);
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}
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// Finally, remove the $sop cell
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cells_to_remove.insert(cell);
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}
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}
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// Actually do the removal now that we aren't iterating
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for (auto cell : cells_to_remove)
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{
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module->remove(cell);
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}
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}
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}
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} Coolrunner2SopPass;
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PRIVATE_NAMESPACE_END
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