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yosys/passes
History
Miodrag Milanovic d5de2a0cdb Make it work on all
2021-11-05 10:51:58 +01:00
..
cmds Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
equiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
fsm Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
hierarchy verilog: use derived module info to elaborate cell connections 2021-10-25 18:25:50 -07:00
memory FfData: some refactoring. 2021-10-07 04:24:06 +02:00
opt FfData: some refactoring. 2021-10-07 04:24:06 +02:00
pmgen Make it work on all 2021-11-05 10:51:58 +01:00
proc proc_dff: Emit $aldff. 2021-10-27 14:14:24 +02:00
sat FfData: some refactoring. 2021-10-07 04:24:06 +02:00
techmap flatten: Keep sigmap around between flatten_cell invocations. 2021-11-02 13:18:15 +01:00
tests Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00