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Code Activity
yosys/tests/sat
History
Clifford Wolf 3b52121d32 now ignore init attributes on non-register wires in sat command
2014-07-05 11:18:38 +02:00
..
.gitignore Added test cases for sat command 2014-02-04 13:43:34 +01:00
asserts.v Added test cases for sat command 2014-02-04 13:43:34 +01:00
asserts.ys Added read_verilog -sv options, added support for bit, logic, 2014-06-12 11:54:20 +02:00
asserts_seq.v Added test cases for sat command 2014-02-04 13:43:34 +01:00
asserts_seq.ys Added read_verilog -sv options, added support for bit, logic, 2014-06-12 11:54:20 +02:00
counters.v Added counters sat test case 2014-02-06 01:00:56 +01:00
counters.ys Added counters sat test case 2014-02-06 01:00:56 +01:00
expose_dff.v Added test cases for expose -evert-dff 2014-02-08 21:31:56 +01:00
expose_dff.ys Added test cases for expose -evert-dff 2014-02-08 21:31:56 +01:00
initval.v now ignore init attributes on non-register wires in sat command 2014-07-05 11:18:38 +02:00
initval.ys now ignore init attributes on non-register wires in sat command 2014-07-05 11:18:38 +02:00
run-test.sh Added test cases for sat command 2014-02-04 13:43:34 +01:00
splice.v Added splice command 2014-02-07 20:30:56 +01:00
splice.ys Added splice command 2014-02-07 20:30:56 +01:00