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yosys/techlibs/common
2019-07-16 12:45:29 -07:00
..
.gitignore
adff2dff.v
cellhelp.py
cells.lib
cmp2lut.v gen_lut to return correctly sized LUT mask 2019-07-16 12:45:29 -07:00
dff2ff.v
gate2lut.v
Makefile.inc
pmux2mux.v
prep.cc Add "wreduce -keepdc", fixes #1016 2019-05-20 15:36:13 +02:00
simcells.v
simlib.v Improve $specrule interface 2019-04-23 22:57:10 +02:00
synth.cc Revert "Add "synth -keepdc" option" 2019-07-09 10:14:23 -07:00
techmap.v