mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
331ac5285f
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.
15 lines
626 B
Text
15 lines
626 B
Text
read_verilog -sv meminit.v
|
|
chparam -set DEPTH_LOG2 3 -set WIDTH 36
|
|
prep
|
|
opt_dff
|
|
prep -rdff
|
|
synth_quicklogic -family qlf_k6n10f -run map_bram:map_bram
|
|
select -assert-none t:$mem_v2 t:$mem
|
|
select -assert-count 1 t:TDP36K
|
|
select -assert-count 1 t:TDP36K a:is_split=0 %i
|
|
select -assert-count 1 t:TDP36K a:was_split_candidate=0 %i
|
|
read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
|
|
prep
|
|
async2sync
|
|
hierarchy -top top
|
|
sim -assert -q -n 12 -clock clk
|