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yosys/tests/memlib
Emil J. Tywoniak eb32507cb5 tests: exclude signorm marker cells from cell-count assertions
$input_port, $output_port and $public are signorm bookkeeping rather than
mapped logic, so assertions counting "every cell" or "every $ cell" have
to subtract them -- as tests/opt/opt_expr_*.ys already do with
`t:$*_port %d t:$public %d`.

The memlib assertions are generated, so the fix goes in generate_mk.py
rather than the generated scripts.

These only differ once a design can still be in signorm mode when the
assertion runs; the subtraction is a no-op otherwise.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
2026-07-21 14:05:18 +02:00
..
.gitignore
generate_mk.py tests: exclude signorm marker cells from cell-count assertions 2026-07-21 14:05:18 +02:00
memlib_9b1B.txt Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
memlib_9b1B.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
memlib_block_sdp.txt
memlib_block_sdp.v
memlib_block_sdp_1clk.txt
memlib_block_sdp_1clk.v
memlib_block_sp.txt
memlib_block_sp.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
memlib_block_sp_full.txt
memlib_block_sp_full.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
memlib_block_tdp.txt
memlib_block_tdp.v
memlib_clock_sdp.txt
memlib_clock_sdp.v
memlib_lut.txt End of file fix 2026-06-23 07:23:41 +02:00
memlib_lut.v
memlib_multilut.txt
memlib_multilut.v
memlib_wide_read.txt
memlib_wide_read.v
memlib_wide_sdp.txt
memlib_wide_sdp.v
memlib_wide_sp.txt
memlib_wide_sp.v
memlib_wide_write.txt
memlib_wide_write.v End of file fix 2026-06-23 07:23:41 +02:00
memlib_wren.txt
memlib_wren.v