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65 lines
1.1 KiB
Verilog
65 lines
1.1 KiB
Verilog
module $__GOWIN_LUTRAM_(...);
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parameter INIT = 64'bx;
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parameter BITS_USED = 0;
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input PORT_W_CLK;
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input [3:0] PORT_W_ADDR;
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input PORT_W_WR_EN;
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input [3:0] PORT_W_WR_DATA;
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input [3:0] PORT_R_ADDR;
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output [3:0] PORT_R_RD_DATA;
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function [15:0] init_slice;
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input integer idx;
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integer i;
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for (i = 0; i < 16; i = i + 1)
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init_slice[i] = INIT[4*i+idx];
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endfunction
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generate
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casez(BITS_USED)
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4'b000z:
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RAM16SDP1 #(
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.INIT_0(init_slice(0)),
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) _TECHMAP_REPLACE_ (
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.WAD(PORT_W_ADDR),
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.RAD(PORT_R_ADDR),
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.DI(PORT_W_WR_DATA[0]),
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.DO(PORT_R_RD_DATA[0]),
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.CLK(PORT_W_CLK),
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.WRE(PORT_W_WR_EN)
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);
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4'b00zz:
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RAM16SDP2 #(
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.INIT_0(init_slice(0)),
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.INIT_1(init_slice(1)),
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) _TECHMAP_REPLACE_ (
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.WAD(PORT_W_ADDR),
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.RAD(PORT_R_ADDR),
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.DI(PORT_W_WR_DATA[1:0]),
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.DO(PORT_R_RD_DATA[1:0]),
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.CLK(PORT_W_CLK),
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.WRE(PORT_W_WR_EN)
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);
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default:
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RAM16SDP4 #(
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.INIT_0(init_slice(0)),
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.INIT_1(init_slice(1)),
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.INIT_2(init_slice(2)),
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.INIT_3(init_slice(3)),
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) _TECHMAP_REPLACE_ (
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.WAD(PORT_W_ADDR),
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.RAD(PORT_R_ADDR),
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.DI(PORT_W_WR_DATA),
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.DO(PORT_R_RD_DATA),
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.CLK(PORT_W_CLK),
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.WRE(PORT_W_WR_EN)
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);
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endcase
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endgenerate
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endmodule
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