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yosys/tests/fmt
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Charlotte 3571bf2c2d fmt: fuzz, remove some unnecessary busywork 
Removing some signed checks and logic where we've already guaranteed the
values to be positive.  Indeed, in these cases, if a negative value got
through (per my realisation in the signed fuzz harness), it would cause
an infinite loop due to flooring division.
2023-08-11 04:46:52 +02:00
..
fuzz fmt: fuzz, remove some unnecessary busywork 2023-08-11 04:46:52 +02:00
.gitignore fmt: add tests for Verilog round trip of format expressions. 2023-08-11 04:46:52 +02:00
always_display.v fmt: add tests for Verilog round trip of format expressions. 2023-08-11 04:46:52 +02:00
always_full.v fmt: %t/$time support 2023-08-11 04:46:52 +02:00
always_full_tb.cc tests: test cxxrtl against iverilog (and uncover bug!) 2023-08-11 04:46:52 +02:00
always_full_tb.v tests: test cxxrtl against iverilog (and uncover bug!) 2023-08-11 04:46:52 +02:00
display_lm.v fmt: rudimentary %m support (= %l) 2023-08-11 04:46:52 +02:00
display_lm_tb.cc fmt: rudimentary %m support (= %l) 2023-08-11 04:46:52 +02:00
initial_display.v fmt: format %t consistently at initial 2023-08-11 04:46:52 +02:00
roundtrip.v fmt: add tests for Verilog round trip of format expressions. 2023-08-11 04:46:52 +02:00
roundtrip_tb.v fmt: add tests for Verilog round trip of format expressions. 2023-08-11 04:46:52 +02:00
run-test.sh fmt: rudimentary %m support (= %l) 2023-08-11 04:46:52 +02:00