Emil J. Tywoniak ae281720cf tests: remove unstable FPGA synthesis result checks		2025-11-12 11:52:04 +01:00
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add_sub.ys
adffs.ys
counter.ys
dffs.ys
fsm.ys	tests: remove unstable FPGA synthesis result checks	2025-11-12 11:52:04 +01:00
latches.ys
logic.ys
mux.ys
run-test.sh	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
tribuf.ys