mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 13:10:51 +00:00
Code Activity
yosys/frontends/vhdl2verilog/Makefile.inc
Clifford Wolf 0a60f95224 Added vhdl2verilog
2014-02-21 18:59:49 +01:00

1 line
46 B
Makefile
Raw Blame History

OBJS += frontends/vhdl2verilog/vhdl2verilog.o
View git blame Copy permalink