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19 lines
240 B
Text
19 lines
240 B
Text
read_verilog -icells << EOT
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module top(...);
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input [1:0] D;
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input C, R;
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output [1:0] Q;
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always @(posedge C, posedge R)
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if (R)
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Q <= 0;
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else
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Q <= D;
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endmodule
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EOT
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proc
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#equiv_opt -assert -async2sync techmap -map +/adff2dff.v
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